Abstract: Carrier scatterings in the inversion channel of MOSFET dominates the carrier mobility and hence drain current. This paper presents an analytical model of the subthreshold drain current incorporating the effective electron mobility model of the pocket implanted nano scale n-MOSFET. The model is developed by assuming two linear pocket profiles at the source and drain edges at the surface and by using the conventional drift-diffusion equation. Effective electron mobility model includes three scattering mechanisms, such as, Coulomb, phonon and surface roughness scatterings as well as ballistic phenomena in the pocket implanted n-MOSFET. The model is simulated for various pocket profile and device parameters as well as for various bias conditions. Simulation results show that the subthreshold drain current data matches the experimental data already published in the literature.
Abstract: The newest semiconductor devices on the market are MOSFET transistors based on the silicon carbide – SiC. This material has exclusive features thanks to which it becomes a better switch than Si – silicon semiconductor switch. There are some special features that need to be understood to enable the device’s use to its full potential. The advantages and differences of SiC MOSFETs in comparison with Si IGBT transistors have been described in first part of this article. Second part describes driver for SiC MOSFET transistor and last part of article represents SiC MOSFET in the application of buck converter (step-down) and design of simple RC snubber.
Abstract: In this paper, a power laterally-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) on In0.53Ga0.47As is presented. The device utilizes a thicker field-oxide with low dielectric constant under the field-plate in order to achieve possible reduction in device capacitances and reduced-surface-field effect. Using 2D numerical simulations, performance of the proposed device is analyzed and compared with that of the conventional LDMOSFET. The proposed structure provides 50% increase in the breakdown voltage, 21% increase in transit frequency, and 72% improvement in figure-of-merit over the conventional device for same cell pitch.
Abstract: This paper presents device simulations on the vertical silicon nanowire tunneling FET (VSiNW TFET). Simulations show that a narrow nanowire and thin gate oxide is required for good performance, which is expected even for conventional MOSFETs. The gate length also needs to be more than the nanowire diameter to prevent short channel effects. An effect more unique to TFET is the need for abrupt source to channel junction, which is shown to improve the performance. The ambipolar effect suppression by reducing drain doping concentration is also explored and shown to have little or no effect on performance.
Abstract: This paper presents a new compact analytical model of
the gate leakage current in high-k based nano scale MOSFET by
assuming a two-step inelastic trap-assisted tunneling (ITAT) process
as the conduction mechanism. This model is based on an inelastic
trap-assisted tunneling (ITAT) mechanism combined with a semiempirical
gate leakage current formulation in the BSIM 4 model. The
gate tunneling currents have been calculated as a function of gate
voltage for different gate dielectrics structures such as HfO2, Al2O3
and Si3N4 with EOT (equivalent oxide thickness) of 1.0 nm. The
proposed model is compared and contrasted with santaurus
simulation results to verify the accuracy of the model and excellent
agreement is found between the analytical and simulated data. It is
observed that proposed analytical model is suitable for different highk
gate dielectrics simply by adjusting two fitting parameters. It was
also shown that gate leakages reduced with the introduction of high-k
gate dielectric in place of SiO2.
Abstract: A vertical SOI-based MOSFET with trench body
structure operated as 1T DRAM cell at various temperatures has been
studied and investigated. Different operation temperatures are
assigned for the device for its performance comparison, thus the
thermal stability is carefully evaluated for the future memory device
applications. Based on the simulation, the vertical SOI-based
MOSFET with trench body structure demonstrates the electrical
characteristics properly and possess conspicuous kink effect at
various operation temperatures. Transient characteristics were also
performed to prove that its programming window values and
retention time behaviors are acceptable when the new 1T DRAM cell
is operated at high operation temperature.
Abstract: Photo-BJMOSFET (Bipolar Junction Metal-Oxide-
Semiconductor Field Effect Transistor) fabricated on SOI film was proposed. ITO film is adopted in the device as gate electrode to reduce
light absorption. Depletion region but not inversion region is formed
in film by applying gate voltage (but low reverse voltage) to achieve
high photo-to-dark-current ratio. Comparisons of photoelectriccharacteristics
executed among VGK=0V, 0.3V, 0.6V, 0.9V and 1.0V
(reverse voltage VAK is equal to 1.0V for total area of 10×10μm2). The
results indicate that the greatest improvement in photo-to-dark-current
ratio is achieved up to 2.38 at VGK=0.6V. In addition,
photo-BJMOSFET is compatible with CMOS integration due to big
input resistance
Abstract: Aggressive scaling of MOS devices requires use of ultra-thin gate oxides to maintain a reasonable short channel effect and to take the advantage of higher density, high speed, lower cost etc. Such thin oxides give rise to high electric fields, resulting in considerable gate tunneling current through gate oxide in nano regime. Consequently, accurate analysis of gate tunneling current is very important especially in context of low power application. In this paper, a simple and efficient analytical model has been developed for channel and source/drain overlap region gate tunneling current through ultra thin gate oxide n-channel MOSFET with inevitable deep submicron effect (DSME).The results obtained have been verified with simulated and reported experimental results for the purpose of validation. It is shown that the calculated tunnel current is well fitted to the measured one over the entire oxide thickness range. The proposed model is suitable enough to be used in circuit simulator due to its simplicity. It is observed that neglecting deep sub-micron effect may lead to large error in the calculated gate tunneling current. It is found that temperature has almost negligible effect on gate tunneling current. It is also reported that gate tunneling current reduces with the increase of gate oxide thickness. The impact of source/drain overlap length is also assessed on gate tunneling current.
Abstract: This paper presents a vertical silicon nanowire n- MOSFET integrated with a CMOS-compatible fully-silicided (FUSI) NiSi2 gate. Devices with nanowire diameter of 50nm show good electrical performance (SS < 70mV/dec, DIBL < 30mV/V, Ion/Ioff > 107). Most significantly, threshold voltage tunability of about 0.2V is shown. Although threshold voltage remains low for the 50nm diameter device, it is expected to become more positive as nanowire diameter reduces.
Abstract: We integrate TiN/Ni/HfO2/Si RRAM cell with a
vertical gate-all-around (GAA) nanowire transistor to achieve
compact 4F2 footprint in a 1T1R configuration. The tip of the Si
nanowire (source of the transistor) serves as bottom electrode of the
memory cell. Fabricated devices with nanowire diameter ~ 50nm
demonstrate ultra-low current/power switching; unipolar switching
with 10μA/30μW SET and 20μA/30μW RESET and bipolar switching
with 20nA/85nW SET and 0.2nA/0.7nW RESET. Further, the
switching current is found to scale with nanowire diameter making the
architecture promising for future scaling.
Abstract: Personnel protection devices are cardinal in safety hazard applications. They are widely used in home, office and in industry environments to reduce the risk of lethal shock to human being and equipment safety. This paper briefly reviews various personnel protection devices also describes the basic working principle of conventional ground fault circuit interrupter (GFCI) or ground fault isolator (GFI), its disadvantages and ways to overcome the disadvantages with solid-state relay (SSR) based GFI with ultrafast response up on fault implemented in printed circuit board. This solid state GFI comprises discrete MOSFET based alternating current (AC) switches, linear optical amplifier, photovoltaic isolator and sense resistor. In conventional GFI, current transformer is employed as a sensing element to detect the difference in current flow between live and neutral conductor. If there is no fault in equipment powered through GFI, due to insulation failure of internal wires and windings of motors, both live and neutral currents will be equal in magnitude and opposite in phase.
Abstract: Carriers scattering in the inversion channel of n-
MOSFET dominates the drain current. This paper presents an effective
electron mobility model for the pocket implanted nano scale
n-MOSFET. The model is developed by using two linear pocket
profiles at the source and drain edges. The channel is divided into
three regions at source, drain and central part of the channel region.
The total number of inversion layer charges is found for these three
regions by numerical integration from source to drain ends and the
number of depletion layer charges is found by using the effective
doping concentration including pocket doping effects. These two
charges are then used to find the effective normal electric field,
which is used to find the effective mobility model incorporating the
three scattering mechanisms, such as, Coulomb, phonon and surface
roughness scatterings as well as the ballistic phenomena for the
pocket implanted nano-scale n-MOSFET. The simulation results show
that the derived mobility model produces the same results as found
in the literatures.
Abstract: This paper presents the doping profile measurement
and characterization technique for the pocket implanted nano scale
n-MOSFET. Scanning capacitance microscopy and atomic force
microscopy have been used to image the extent of lateral dopant
diffusion in MOS structures. The data are capacitance vs. voltage
measurements made on a nano scale device. The technique is nondestructive
when imaging uncleaved samples. Experimental data from
the published literature are presented here on actual, cleaved device
structures which clearly indicate the two-dimensional dopant profile
in terms of a spatially varying modulated capacitance signal. Firstorder
deconvolution indicates the technique has much promise for
the quantitative characterization of lateral dopant profiles. The pocket
profile is modeled assuming the linear pocket profiles at the source
and drain edges. From the model, the effective doping concentration
is found to use in modeling and simulation results of the various
parameters of the pocket implanted nano scale n-MOSFET. The
potential of the technique to characterize important device related
phenomena on a local scale is also discussed.
Abstract: We propose photo-BJMOSFET (Bipolar Junction Metal-Oxide-Semiconductor Field Effect Transistor) fabricated on SOI film. ITO film is adopted in the device as gate electrode to reduce light absorption. I-V characteristics of photo-BJMOSFET obtained in dark (dark current) and under 570nm illumination (photo current) are studied furthermore to achieve high photo-to-dark-current contrast ratio. Two variables in the calculation were the channel length and the thickness of the film which were set equal to six different values, i.e., L=2, 4, 6, 8, 10, and 12μm and three different values, i.e., dsi =100, 200 and 300nm, respectively. The results indicate that the greatest photo-to-dark-current contrast ratio is achieved with L=10μm and dsi=200 nm at VGK=0.6V.
Abstract: In this paper the features of multiple material gate
silicon-on-insulator MOSFETs are presented and compared with
single material gate silicon-on-insulator MOSFET structures. The
results indicate that the multiple material gate structures reduce short
channel effects such as drain induce barrier lowering, hot electron
effect and better current characteristics in comparison with single
material structures
Abstract: This paper presents a threshold voltage model of pocket implanted sub-100 nm n-MOSFETs incorporating the drain and substrate bias effects using two linear pocket profiles. Two linear equations are used to simulate the pocket profiles along the channel at the surface from the source and drain edges towards the center of the n-MOSFET. Then the effective doping concentration is derived and is used in the threshold voltage equation that is obtained by solving the Poisson-s equation in the depletion region at the surface. Simulated threshold voltages for various gate lengths fit well with the experimental data already published in the literature. The simulated result is compared with the two other pocket profiles used to derive the threshold voltage models of n-MOSFETs. The comparison shows that the linear model has a simple compact form that can be utilized to study and characterize the pocket implanted advanced ULSI devices.
Abstract: This paper proposes a zero-voltage transition (ZVT) PWM synchronous buck converter, which is designed to operate at low output voltage and high efficiency typically required for portable systems. To make the DC-DC converter efficient at lower voltage, synchronous converter is an obvious choice because of lower conduction loss in the diode. The high-side MOSFET is dominated by the switching losses and it is eliminated by the soft switching technique. Additionally, the resonant auxiliary circuit designed is also devoid of the switching losses. The suggested procedure ensures an efficient converter. Theoretical analysis, computer simulation, and experimental results are presented to explain the proposed schemes.
Abstract: Vertical Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is believed to suppress various short channel effect problems. The gate to channel coupling in vertical DG-MOSFET are doubled, thus resulting in higher current density. By having two gates, both gates are able to control the channel from both sides and possess better electrostatic control over the channel. In order to ensure that the transistor possess a superb turn-off characteristic, the subs-threshold swing (SS) must be kept at minimum value (60-90mV/dec). By utilizing SILVACO TCAD software, an n-channel vertical DG-MOSFET was successfully designed while keeping the sub-threshold swing (SS) value as minimum as possible. From the observation made, the value of sub-threshold swing (SS) was able to be varied by adjusting the height of the silicon pillar. The minimum value of sub-threshold swing (SS) was found to be 64.7mV/dec with threshold voltage (VTH) of 0.895V. The ideal height of the vertical DG-MOSFET pillar was found to be at 0.265 µm.
Abstract: A new low-voltage floating gate MOSFET (FGMOS)
based squarer using square law characteristic of the FGMOS is
proposed in this paper. The major advantages of the squarer are simplicity,
rail-to-rail input dynamic range, low total harmonic distortion,
and low power consumption. The proposed circuit is biased without
body effect. The circuit is designed and simulated using SPICE in
0.25μm CMOS technology. The squarer is operated at the supply
voltages of ±0.75V . The total harmonic distortion (THD) for the
input signal 0.75Vpp at 25 KHz, and maximum power consumption
were found to be less than 1% and 319μW respectively.
Abstract: The floating body effect is a serious problem for the
PDSOI MOSFET, and the H-gate layout is frequently used as the body contact to eliminate this effect. Unfortunately, most of the standard commercial SOI MOSFET model is for the device with finger gate, the
necessity of the new models for the H-gate device arises. A simulation
model for the H-gate PDSOI MOSFET is proposed based on the 0.35μm PDSOI process developed by the Institute of Microelectronics
of the Chinese Academy of Sciences (IMECAS), and then the model is well verified by the ring-oscillator.