Trap Assisted Tunneling Model for Gate Current in Nano Scale MOSFET with High-K Gate Dielectrics
This paper presents a new compact analytical model of
the gate leakage current in high-k based nano scale MOSFET by
assuming a two-step inelastic trap-assisted tunneling (ITAT) process
as the conduction mechanism. This model is based on an inelastic
trap-assisted tunneling (ITAT) mechanism combined with a semiempirical
gate leakage current formulation in the BSIM 4 model. The
gate tunneling currents have been calculated as a function of gate
voltage for different gate dielectrics structures such as HfO2, Al2O3
and Si3N4 with EOT (equivalent oxide thickness) of 1.0 nm. The
proposed model is compared and contrasted with santaurus
simulation results to verify the accuracy of the model and excellent
agreement is found between the analytical and simulated data. It is
observed that proposed analytical model is suitable for different highk
gate dielectrics simply by adjusting two fitting parameters. It was
also shown that gate leakages reduced with the introduction of high-k
gate dielectric in place of SiO2.
[1] Buchanan, D., IBM J. Res. Develop. (1999) 43, 245
[2] J. A. Felix, D. M. Fleetwood, R. D. Schrimpf, J. G. Hong, G. Lucovsky, J.
R. Schwank, and M. R. Shaneyfelt, "Total-dose radiation response of
hafnium- silicate capacitors," IEEE Transactions on Nuclear Science,
vol. 49, no. 6, pp. 3191-3196, Dec. 2002.
[3] J. A. Felix, M. R. Shaneyfelt, D. M. Fleetwood, T. L. Meisenheimer, J. R.
Schwank, R. D. Schrimpf, P. E. Dodd, E. P. Gusev, and C. D- Emic,
"Radiation-induced charge trapping in thin AlO
3
/SiO
x
N
y
/Si(100) gate
dielectric stacks," IEEE Transactions on Nuclear Science, vol. 50, no. 6,
pp. 1910-1918, Dec. 2003.
[4] M. Houssa, G. Pourtois, M. M. Heyns and A. Stesmans, "Defect
generation in high ╬║ gate dielectric stacks under electrical stress: the
impact of hydrogen," Journal of Physics: Condensed Matter, vol.17, pp.
s2075-s2088, 2005
[5] E. P. Gusev, E. Cartier, D. A. Buchanan, M. Gribelyuk, M. Copel, H.
Okorn-Schmidt, and C. D-Emic, "Ultrathin high-╬║ metal oxides on
silicon: processing, characterization and integration issues,"
Microelectronic Engineering, vol. 59, no.1-4, pp. 341-349, 2001.
[6] G. D. Wilk, R. M. Wallace, and J. M. Anthony, "High-╬║ gate dielectrics:
current status and materials properties considerations," Applied Physics
Letters, vol. 89, pp. 5243-5275, 2001.
[7] B. H. Lee, L. Kang, W. J. Qi, R. Nieh, Y. Jeon, K. Onishi, and J. C. Lee,
"Ultrathin hafnium oxide with low leakage and excellent reliability for
alternative gate dielectric application," IEEE International Electron
Devices Meeting (IEDM) Technical Digest, pp.133-135, 1999.
[8] Lee, W., et al., Tech. Dig. IEDM (1998), 605.
[9] Wilk, G. D., and Wallace, R. M., Appl. Phys. Lett. (2000) 76, 112
[10] Qi, W.-J., et al., Tech. Dig. IEDM (1999), 145
[11] Lee, B. H., et al., Appl. Phys. Lett. (2000) 76, 1926.
[12] Buchanan, D. A., et al., Tech. Dig. IEDM (2000), 223.
[13] E. P. Gusev, C. Cabral, Jr., B. P. Linder, Y.H. Kim, K. Maitra, E. Cartier,
and Y. Zhang, "Advanced gate stacks with fully silicided (FUSI) gates
and high-╬║ dielectrics: enhanced performance at reduced gate leakage,"
IEEE International Electron Devices Meeting (IEDM) Technical Digest,
pp. 79-82, Dec. 2004.
[14] A. Aziz, K. Kassami, Ka. Kassami, F. Olivie, " Modelling of the
influence of charges trapped in the oxide on the I(Vg) characteristics of
metal-ultra-thin oxide-semiconductor structures." Semicond. Sci.
Technol. 19 (2004) 877-884.
[15] D. Heh, C.-D. Young, G.-A. Brown, P.-Y. Hung, E.-M. Vogel, J.-
B.Bernstein, "Spatial distribution of trapping centers in HfO2/SiO2 ."
Appl. Phys. Lett. 88 (2006) 152907.
[16] D. J. DiMaria and E. Cartier, Journal of Applied. Physics. 78,3883,
(1995)
[17] V. Fomenko, E. P. Gusev, E. Borguet, "Optical second harmonic
generation studies of ultrathin high-╬║ dielectric stacks," Journal of
Applied Physics, vol. 97, article no. 083711, 2005.
[18] A. Palma, F.Jime'nez-Molinos,F. Ga 'miz, P. Cartujo, and J. A. Lo 'pez-
Villanueva, "Direct and trap-assisted elastic tunneling through ultrathin
gate oxides," J. Appl. Phys., Vol. 91, No. 8, April 2002, pp 5116-5124
[19] Eric M. Vogel, Khaled Z. Ahmed, Brian Hornung, W. Kirklen Henson,
Peter K. McLarty, Gerry Lucovsky, John R. Hauserand Jimmie J.
Wortman, " Modeled Tunnel Current for High Dielectric Constant
Dielectrics." IEEE Transactions on Electron Devices, Vol. 45, No. 6, pp
1350-1355, June 1998.
[20] Mudanai S, Fan Y, Ouyang Q, Tasch AF, Banerjee SK., "Modeling of
direct tunneling current through gate dielectric stacks. IEEE
Transaction on Electron Device 2000;Vol 47, No (10):1851.
[21] Wei Wang , Ning Gu, J.P. Sun, P. Mazumder, "Gate current modeling of
high-k stack nanoscale MOSFETs." Solid-State Electronics 50 (2006)
1489-1494ÔÇöpaper 20
[22] Huixian Wu, Yijie (Sandy) Zhao, Marvin H. White , "Quantum
mechanical modeling of MOSFET gate leakage for high-k gate
dielectrics." Solid-State Electronics 50 (2006) 1164-1169.
[23] A. Bouazra, S. Abdi-Ben Vasrallah, A. Poncet and M. Said, " Current
tunneling through MOS devices." Materials Science and Engineering: C,
Vol. 28, Issues 5-6, July 2008, pp 662-665.
[24] W.-C. Lee and C. Hu, "Modeling gate and substrate currents due to
conduction- and valence-band electron and hole tunneling," Symposium
on VLSI Technology Digest of Technical Papers, pp. 198, 2000.
[25] W.-C. Lee and C. Hu, "Modeling CMOS tunneling currents through
ultrathin gate oxide due to conduction- and valence-band electron and
hole tunneling," IEEE Trans. Electron Devices, vol. 48, pp. 1366-1373,
June 2001
[26] L. E. Calvet, R. G. Wheeler, and M. A. Reed, Applied Physics Letters,
vol 80, No 10, March 2002.
[27] Pr_egaldiny , Christophe Lallement, Daniel Mathiot," Accounting for
quantum mechanical effects from accumulation to inversion, in a fully
analytical surface potential-based MOSFET model," Solid-State
Electronics 48 (2004) 781-787
[28] Taur, Y., and Ning, T.H.: ÔÇÿFundamentals of modern VLSI devices-
(Cambridge University Press, New York, 1998).
[29] Chang-Hoon Choi, P. R. Chidambaram, Rajesh Khamankar, Charles F.
Machala, Zhiping Yu, and Robert W. Dutton, "Dopant Profile and Gate
Geometric Effects on Polysilicon Gate Depletion in Scaled MOS,"IEEE
Transactions on Electron Devices, vol. 49, no. 7, July 2002
[30] Steve Shao-Shiun Chung and Tung-Chi Li, IEEE Transactions On
Electron Devices, Vol. 39, No. 3, March 1992
[31] ISE TCAD: Synopsys Santaurus Device User Manual, 1995-2005,
Synopsys, Mountain View, CA.
[32] ISE TCAD: Synopsys Santaurus Device simulator
[33] Hitender Kumar Tyagi, and P. J. George, " Tunneling currents through
ultra thin HfO2/Al2O3/HfO2 triple layer gate dielectrics for advanced MIS
devices", J Mater Sci: Mater Electron (2008)19 :902-907.
[34] S. Y. Chen, H. W. Chen, F. C. Chiu, C. H. Liu, Z. Y. Hsieh, H. S. Huang
and H. L. Hwang, "Interfacial and Electrical Characterization of HfO2-
Gated MOSCs and MOSFETs by C-V and Gated-Diode Method", ECS
Trans., vol 16, No. 5 October, 2008 , pp. 131-138.
[35] V.E. Drozd, A.P. Baraban and I.O. Nikiforova, "Electrical properties of
SiÔÇöAl2O3 structures grown by ML-ALE" , Applied Surface Science,
Volumes 82-83, 2 December 1994, Pages 583-586
[36] Park, Y. C. Jackson, W. B. Johnson, N. M. Hagstrom, S. B. ," Spatial
profiling of electron traps in silicon nitride thin films ", Journal of
Applied Physics, vol 68, No 10, Nov 1990, pp 5212 - 5221
[37] A.V. Vishnyakov , Yu.N. Novikov, V.A. Gritsenko , K.A. Nasyrov, "The
charge transport mechanism in silicon nitride: Multi-phonon trap
ionization", Solid-State Electronics vol 53, No 3, March 2009, pp
251-255.
[38] T. P. Ma, "Making Silicon Nitride Film a Viable Gate Dielectric", IEEE
Transactions on Electron Devices, vol. 45, No. 3, March 1998, pp 680-
690
[39] Katsuyuki Sekine, Yuji Saito, Masaki Hirayama, and Tadahiro Ohmi,
"Highly Robust Ultrathin Silicon Nitride Films Grown at Low
Temperature by Microwave-Excitation High-Density Plasma for Giga
Scale Integration", IEEE Transactions on Electron Devices, Vol. 47, No.
7, July 2000, pp 1370-1374.
[1] Buchanan, D., IBM J. Res. Develop. (1999) 43, 245
[2] J. A. Felix, D. M. Fleetwood, R. D. Schrimpf, J. G. Hong, G. Lucovsky, J.
R. Schwank, and M. R. Shaneyfelt, "Total-dose radiation response of
hafnium- silicate capacitors," IEEE Transactions on Nuclear Science,
vol. 49, no. 6, pp. 3191-3196, Dec. 2002.
[3] J. A. Felix, M. R. Shaneyfelt, D. M. Fleetwood, T. L. Meisenheimer, J. R.
Schwank, R. D. Schrimpf, P. E. Dodd, E. P. Gusev, and C. D- Emic,
"Radiation-induced charge trapping in thin AlO
3
/SiO
x
N
y
/Si(100) gate
dielectric stacks," IEEE Transactions on Nuclear Science, vol. 50, no. 6,
pp. 1910-1918, Dec. 2003.
[4] M. Houssa, G. Pourtois, M. M. Heyns and A. Stesmans, "Defect
generation in high ╬║ gate dielectric stacks under electrical stress: the
impact of hydrogen," Journal of Physics: Condensed Matter, vol.17, pp.
s2075-s2088, 2005
[5] E. P. Gusev, E. Cartier, D. A. Buchanan, M. Gribelyuk, M. Copel, H.
Okorn-Schmidt, and C. D-Emic, "Ultrathin high-╬║ metal oxides on
silicon: processing, characterization and integration issues,"
Microelectronic Engineering, vol. 59, no.1-4, pp. 341-349, 2001.
[6] G. D. Wilk, R. M. Wallace, and J. M. Anthony, "High-╬║ gate dielectrics:
current status and materials properties considerations," Applied Physics
Letters, vol. 89, pp. 5243-5275, 2001.
[7] B. H. Lee, L. Kang, W. J. Qi, R. Nieh, Y. Jeon, K. Onishi, and J. C. Lee,
"Ultrathin hafnium oxide with low leakage and excellent reliability for
alternative gate dielectric application," IEEE International Electron
Devices Meeting (IEDM) Technical Digest, pp.133-135, 1999.
[8] Lee, W., et al., Tech. Dig. IEDM (1998), 605.
[9] Wilk, G. D., and Wallace, R. M., Appl. Phys. Lett. (2000) 76, 112
[10] Qi, W.-J., et al., Tech. Dig. IEDM (1999), 145
[11] Lee, B. H., et al., Appl. Phys. Lett. (2000) 76, 1926.
[12] Buchanan, D. A., et al., Tech. Dig. IEDM (2000), 223.
[13] E. P. Gusev, C. Cabral, Jr., B. P. Linder, Y.H. Kim, K. Maitra, E. Cartier,
and Y. Zhang, "Advanced gate stacks with fully silicided (FUSI) gates
and high-╬║ dielectrics: enhanced performance at reduced gate leakage,"
IEEE International Electron Devices Meeting (IEDM) Technical Digest,
pp. 79-82, Dec. 2004.
[14] A. Aziz, K. Kassami, Ka. Kassami, F. Olivie, " Modelling of the
influence of charges trapped in the oxide on the I(Vg) characteristics of
metal-ultra-thin oxide-semiconductor structures." Semicond. Sci.
Technol. 19 (2004) 877-884.
[15] D. Heh, C.-D. Young, G.-A. Brown, P.-Y. Hung, E.-M. Vogel, J.-
B.Bernstein, "Spatial distribution of trapping centers in HfO2/SiO2 ."
Appl. Phys. Lett. 88 (2006) 152907.
[16] D. J. DiMaria and E. Cartier, Journal of Applied. Physics. 78,3883,
(1995)
[17] V. Fomenko, E. P. Gusev, E. Borguet, "Optical second harmonic
generation studies of ultrathin high-╬║ dielectric stacks," Journal of
Applied Physics, vol. 97, article no. 083711, 2005.
[18] A. Palma, F.Jime'nez-Molinos,F. Ga 'miz, P. Cartujo, and J. A. Lo 'pez-
Villanueva, "Direct and trap-assisted elastic tunneling through ultrathin
gate oxides," J. Appl. Phys., Vol. 91, No. 8, April 2002, pp 5116-5124
[19] Eric M. Vogel, Khaled Z. Ahmed, Brian Hornung, W. Kirklen Henson,
Peter K. McLarty, Gerry Lucovsky, John R. Hauserand Jimmie J.
Wortman, " Modeled Tunnel Current for High Dielectric Constant
Dielectrics." IEEE Transactions on Electron Devices, Vol. 45, No. 6, pp
1350-1355, June 1998.
[20] Mudanai S, Fan Y, Ouyang Q, Tasch AF, Banerjee SK., "Modeling of
direct tunneling current through gate dielectric stacks. IEEE
Transaction on Electron Device 2000;Vol 47, No (10):1851.
[21] Wei Wang , Ning Gu, J.P. Sun, P. Mazumder, "Gate current modeling of
high-k stack nanoscale MOSFETs." Solid-State Electronics 50 (2006)
1489-1494ÔÇöpaper 20
[22] Huixian Wu, Yijie (Sandy) Zhao, Marvin H. White , "Quantum
mechanical modeling of MOSFET gate leakage for high-k gate
dielectrics." Solid-State Electronics 50 (2006) 1164-1169.
[23] A. Bouazra, S. Abdi-Ben Vasrallah, A. Poncet and M. Said, " Current
tunneling through MOS devices." Materials Science and Engineering: C,
Vol. 28, Issues 5-6, July 2008, pp 662-665.
[24] W.-C. Lee and C. Hu, "Modeling gate and substrate currents due to
conduction- and valence-band electron and hole tunneling," Symposium
on VLSI Technology Digest of Technical Papers, pp. 198, 2000.
[25] W.-C. Lee and C. Hu, "Modeling CMOS tunneling currents through
ultrathin gate oxide due to conduction- and valence-band electron and
hole tunneling," IEEE Trans. Electron Devices, vol. 48, pp. 1366-1373,
June 2001
[26] L. E. Calvet, R. G. Wheeler, and M. A. Reed, Applied Physics Letters,
vol 80, No 10, March 2002.
[27] Pr_egaldiny , Christophe Lallement, Daniel Mathiot," Accounting for
quantum mechanical effects from accumulation to inversion, in a fully
analytical surface potential-based MOSFET model," Solid-State
Electronics 48 (2004) 781-787
[28] Taur, Y., and Ning, T.H.: ÔÇÿFundamentals of modern VLSI devices-
(Cambridge University Press, New York, 1998).
[29] Chang-Hoon Choi, P. R. Chidambaram, Rajesh Khamankar, Charles F.
Machala, Zhiping Yu, and Robert W. Dutton, "Dopant Profile and Gate
Geometric Effects on Polysilicon Gate Depletion in Scaled MOS,"IEEE
Transactions on Electron Devices, vol. 49, no. 7, July 2002
[30] Steve Shao-Shiun Chung and Tung-Chi Li, IEEE Transactions On
Electron Devices, Vol. 39, No. 3, March 1992
[31] ISE TCAD: Synopsys Santaurus Device User Manual, 1995-2005,
Synopsys, Mountain View, CA.
[32] ISE TCAD: Synopsys Santaurus Device simulator
[33] Hitender Kumar Tyagi, and P. J. George, " Tunneling currents through
ultra thin HfO2/Al2O3/HfO2 triple layer gate dielectrics for advanced MIS
devices", J Mater Sci: Mater Electron (2008)19 :902-907.
[34] S. Y. Chen, H. W. Chen, F. C. Chiu, C. H. Liu, Z. Y. Hsieh, H. S. Huang
and H. L. Hwang, "Interfacial and Electrical Characterization of HfO2-
Gated MOSCs and MOSFETs by C-V and Gated-Diode Method", ECS
Trans., vol 16, No. 5 October, 2008 , pp. 131-138.
[35] V.E. Drozd, A.P. Baraban and I.O. Nikiforova, "Electrical properties of
SiÔÇöAl2O3 structures grown by ML-ALE" , Applied Surface Science,
Volumes 82-83, 2 December 1994, Pages 583-586
[36] Park, Y. C. Jackson, W. B. Johnson, N. M. Hagstrom, S. B. ," Spatial
profiling of electron traps in silicon nitride thin films ", Journal of
Applied Physics, vol 68, No 10, Nov 1990, pp 5212 - 5221
[37] A.V. Vishnyakov , Yu.N. Novikov, V.A. Gritsenko , K.A. Nasyrov, "The
charge transport mechanism in silicon nitride: Multi-phonon trap
ionization", Solid-State Electronics vol 53, No 3, March 2009, pp
251-255.
[38] T. P. Ma, "Making Silicon Nitride Film a Viable Gate Dielectric", IEEE
Transactions on Electron Devices, vol. 45, No. 3, March 1998, pp 680-
690
[39] Katsuyuki Sekine, Yuji Saito, Masaki Hirayama, and Tadahiro Ohmi,
"Highly Robust Ultrathin Silicon Nitride Films Grown at Low
Temperature by Microwave-Excitation High-Density Plasma for Giga
Scale Integration", IEEE Transactions on Electron Devices, Vol. 47, No.
7, July 2000, pp 1370-1374.
@article{"International Journal of Electrical, Electronic and Communication Sciences:64941", author = "Ashwani K. Rana and Narottam Chand and Vinod Kapoor", title = "Trap Assisted Tunneling Model for Gate Current in Nano Scale MOSFET with High-K Gate Dielectrics", abstract = "This paper presents a new compact analytical model of
the gate leakage current in high-k based nano scale MOSFET by
assuming a two-step inelastic trap-assisted tunneling (ITAT) process
as the conduction mechanism. This model is based on an inelastic
trap-assisted tunneling (ITAT) mechanism combined with a semiempirical
gate leakage current formulation in the BSIM 4 model. The
gate tunneling currents have been calculated as a function of gate
voltage for different gate dielectrics structures such as HfO2, Al2O3
and Si3N4 with EOT (equivalent oxide thickness) of 1.0 nm. The
proposed model is compared and contrasted with santaurus
simulation results to verify the accuracy of the model and excellent
agreement is found between the analytical and simulated data. It is
observed that proposed analytical model is suitable for different highk
gate dielectrics simply by adjusting two fitting parameters. It was
also shown that gate leakages reduced with the introduction of high-k
gate dielectric in place of SiO2.", keywords = "Analytical model, High-k gate dielectrics, inelastic
trap assisted tunneling, metal–oxide–semiconductor (MOS) devices.", volume = "3", number = "3", pages = "574-8", }
