Abstract: This paper presents a vertical silicon nanowire n- MOSFET integrated with a CMOS-compatible fully-silicided (FUSI) NiSi2 gate. Devices with nanowire diameter of 50nm show good electrical performance (SS < 70mV/dec, DIBL < 30mV/V, Ion/Ioff > 107). Most significantly, threshold voltage tunability of about 0.2V is shown. Although threshold voltage remains low for the 50nm diameter device, it is expected to become more positive as nanowire diameter reduces.
Abstract: In this paper, we present a vertical wire NMOS
device fabricated using CMOS compatible processes. The
impact of temperature on various device parameters is
investigated in view of usual increase in surrounding
temperature with device density.