Linear Pocket Profile based Threshold Voltage Model for sub-100 nm n-MOSFET
This paper presents a threshold voltage model of pocket implanted sub-100 nm n-MOSFETs incorporating the drain and substrate bias effects using two linear pocket profiles. Two linear equations are used to simulate the pocket profiles along the channel at the surface from the source and drain edges towards the center of the n-MOSFET. Then the effective doping concentration is derived and is used in the threshold voltage equation that is obtained by solving the Poisson-s equation in the depletion region at the surface. Simulated threshold voltages for various gate lengths fit well with the experimental data already published in the literature. The simulated result is compared with the two other pocket profiles used to derive the threshold voltage models of n-MOSFETs. The comparison shows that the linear model has a simple compact form that can be utilized to study and characterize the pocket implanted advanced ULSI devices.
[1] S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York, USA:
John Wiley & Sons, 1981, ch. 8.
[2] M. Miura-Mattausch, M. Suetake, H. J. Mattausch, S. Kumashiro,
N. Shigyo, S. Oganaka, and N. Nakayama, "Physical modeling of the
reverse short channel effect for circuit simulation," IEEE Transactions
on Electron Devices, vol. 48, pp. 2449-2452, Oct. 2001.
[3] H. E. Ghitani, S. Sadik, and A. H.Shousha, "Two dimensional analytical
modeling of short channel MOS transistors," International Journal of
Electronics, vol. 81, pp. 517-524, 1996.
[4] K. Y. Lim and X. Zhou, "Modeling of threshold voltage with nonuniform
substrate doping," in Proceedings of the IEEE International
Conference on Semiconductor Electronics (ICSE 1998), Malaysia, 1998,
pp. 27-31.
[5] B. Yu, C. H. Wann, E. D. Nowak, K. Noda, and C. Hu, "Short channel
effect improved by lateral channel engineering in deep-submicrometer
MOSFETs," IEEE Transactions on Electron Devices, vol. 44, pp. 627-
633, Apr. 1997.
[6] B. Yu, H. Wang, O. Millic, Q. Xiang, W. Wang, J. X. An, and M. R. Lin,
"50 nm gate length CMOS transistor with super-halo: Design, process
and reliability," IEDM Technical Digest, pp. 653-656, 1999.
[7] K. M. Cao, W. Liu, X. Jin, K. Vasant, K. Green, J. Krick, T. Vrotsos,
and C. Hu, "Modeling of pocket implanted MOSFETs for anomalous
analog behavior," IEDM Technical Digest, pp. 171-174, 1999.
[8] Y. S. Pang and J. R. Brews, "Models for subthreshold and above
subthreshold currents in 0.1 ╬╝m pocket n-MOSFETs for low voltage
applications," IEEE Transactions on Electron Devices, vol. 49, pp. 832-
839, May 2002.
[9] Y. Cheng, T. Sugii, K. Chen, and C. Hu, "Modeling of small size
MOSFETs with reverse short channel and narrow width effects for
circuit simulation," Solid State Electronics, vol. 41, pp. 1227-1231,
1997.
[10] M. K. Khanna, M. C. Thomas, R. S. Gupta, and S. Haldar, "An
analytical model for anomalous threshold voltage behavior of short
channel MOSFETs," Solid State Electronics, vol. 41, pp. 1386-1388,
1997.
[11] Y. Taur and E. J. Nowak, "CMOS devices below 0.1 ╬╝m; how high will
go?" IEDM Technical Digest, pp. 215-218, 1997.
[12] K. N. Ratnakumar and J. D. Meindl, "Short-channel MOST threshold
voltage model," IEEE Journal of Solid State Circuits, vol. 17, pp. 937-
948, Oct. 1982.
[13] X. Zhou, K. Y. Lim, and D. Lim, "Physics-based threshold voltage
modeling with reverse short channel effect," Journal of Modeling and
Simulation of Microsystems, vol. 2, no. 1, pp. 51-56, 1999.
[14] "A general approach to compact threshold voltage formulation
based on 2-D numerical simulation and experimental correlation for
deep-submicron ulsi technology development," IEEE Transactions on
Electron Devices, vol. 47, no. 1, pp. 214-221, Jan. 2000.
[15] M. H. Bhuyan, F. Ferdous, and Q. D. M. Khosru, "A threshold voltage
model for sub-100 nm pocket implanted NMOSFET," in Proceedings
of the 4th IEEE International Conference on Electrical and Computer
Engineering (ICECE 2006), Dhaka, Bangladesh, Dec. 2006, pp. 522-
525.
[1] S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York, USA:
John Wiley & Sons, 1981, ch. 8.
[2] M. Miura-Mattausch, M. Suetake, H. J. Mattausch, S. Kumashiro,
N. Shigyo, S. Oganaka, and N. Nakayama, "Physical modeling of the
reverse short channel effect for circuit simulation," IEEE Transactions
on Electron Devices, vol. 48, pp. 2449-2452, Oct. 2001.
[3] H. E. Ghitani, S. Sadik, and A. H.Shousha, "Two dimensional analytical
modeling of short channel MOS transistors," International Journal of
Electronics, vol. 81, pp. 517-524, 1996.
[4] K. Y. Lim and X. Zhou, "Modeling of threshold voltage with nonuniform
substrate doping," in Proceedings of the IEEE International
Conference on Semiconductor Electronics (ICSE 1998), Malaysia, 1998,
pp. 27-31.
[5] B. Yu, C. H. Wann, E. D. Nowak, K. Noda, and C. Hu, "Short channel
effect improved by lateral channel engineering in deep-submicrometer
MOSFETs," IEEE Transactions on Electron Devices, vol. 44, pp. 627-
633, Apr. 1997.
[6] B. Yu, H. Wang, O. Millic, Q. Xiang, W. Wang, J. X. An, and M. R. Lin,
"50 nm gate length CMOS transistor with super-halo: Design, process
and reliability," IEDM Technical Digest, pp. 653-656, 1999.
[7] K. M. Cao, W. Liu, X. Jin, K. Vasant, K. Green, J. Krick, T. Vrotsos,
and C. Hu, "Modeling of pocket implanted MOSFETs for anomalous
analog behavior," IEDM Technical Digest, pp. 171-174, 1999.
[8] Y. S. Pang and J. R. Brews, "Models for subthreshold and above
subthreshold currents in 0.1 ╬╝m pocket n-MOSFETs for low voltage
applications," IEEE Transactions on Electron Devices, vol. 49, pp. 832-
839, May 2002.
[9] Y. Cheng, T. Sugii, K. Chen, and C. Hu, "Modeling of small size
MOSFETs with reverse short channel and narrow width effects for
circuit simulation," Solid State Electronics, vol. 41, pp. 1227-1231,
1997.
[10] M. K. Khanna, M. C. Thomas, R. S. Gupta, and S. Haldar, "An
analytical model for anomalous threshold voltage behavior of short
channel MOSFETs," Solid State Electronics, vol. 41, pp. 1386-1388,
1997.
[11] Y. Taur and E. J. Nowak, "CMOS devices below 0.1 ╬╝m; how high will
go?" IEDM Technical Digest, pp. 215-218, 1997.
[12] K. N. Ratnakumar and J. D. Meindl, "Short-channel MOST threshold
voltage model," IEEE Journal of Solid State Circuits, vol. 17, pp. 937-
948, Oct. 1982.
[13] X. Zhou, K. Y. Lim, and D. Lim, "Physics-based threshold voltage
modeling with reverse short channel effect," Journal of Modeling and
Simulation of Microsystems, vol. 2, no. 1, pp. 51-56, 1999.
[14] "A general approach to compact threshold voltage formulation
based on 2-D numerical simulation and experimental correlation for
deep-submicron ulsi technology development," IEEE Transactions on
Electron Devices, vol. 47, no. 1, pp. 214-221, Jan. 2000.
[15] M. H. Bhuyan, F. Ferdous, and Q. D. M. Khosru, "A threshold voltage
model for sub-100 nm pocket implanted NMOSFET," in Proceedings
of the 4th IEEE International Conference on Electrical and Computer
Engineering (ICECE 2006), Dhaka, Bangladesh, Dec. 2006, pp. 522-
525.
@article{"International Journal of Electrical, Electronic and Communication Sciences:60674", author = "Muhibul Haque Bhuyan and Quazi Deen Mohd Khosru", title = "Linear Pocket Profile based Threshold Voltage Model for sub-100 nm n-MOSFET", abstract = "This paper presents a threshold voltage model of pocket implanted sub-100 nm n-MOSFETs incorporating the drain and substrate bias effects using two linear pocket profiles. Two linear equations are used to simulate the pocket profiles along the channel at the surface from the source and drain edges towards the center of the n-MOSFET. Then the effective doping concentration is derived and is used in the threshold voltage equation that is obtained by solving the Poisson-s equation in the depletion region at the surface. Simulated threshold voltages for various gate lengths fit well with the experimental data already published in the literature. The simulated result is compared with the two other pocket profiles used to derive the threshold voltage models of n-MOSFETs. The comparison shows that the linear model has a simple compact form that can be utilized to study and characterize the pocket implanted advanced ULSI devices.
", keywords = "Linear pocket profile, pocket implantation, nMOSFET,threshold voltage, short channel effect (SCE), reverse short channeleffect (RSCE).", volume = "4", number = "8", pages = "1237-6", }
