Vertical Silicon Nanowire MOSFET With A Fully-Silicided (FUSI) NiSi2 Gate
This paper presents a vertical silicon nanowire n- MOSFET integrated with a CMOS-compatible fully-silicided (FUSI) NiSi2 gate. Devices with nanowire diameter of 50nm show good electrical performance (SS < 70mV/dec, DIBL < 30mV/V, Ion/Ioff > 107). Most significantly, threshold voltage tunability of about 0.2V is shown. Although threshold voltage remains low for the 50nm diameter device, it is expected to become more positive as nanowire diameter reduces.
[1] S. Bangsaruntip, et al., "High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling", in IEDM Tech. Dig., 2009, pp. 297-300.
[2] N. Singh, et al., "Si, SiGe nanowire devices by top-down technology
and their applications," IEEE TED, vol. 55, no. 11, pp. 3107-3118, Nov.
2008.
[3] S. D. Suk, et al., "High Performance 5nm radius Twin Silicon Nanowire
MOSFET (TSNWFET) : Fabrication on Bulk Si Wafer, Characteristics,
and Reliability," in IEDM Tech. Dig., 2005, pp. 717-720.
[4] B. Yang, et al., "Vertical silicon-nanowire formation and gate-all around
MOSFET," IEEE EDL, vol. 29, no. 7, pp. 791-794, Jul. 2008.
[5] J. Goldberger, et al., "Silicon Vertically Integrated Nanowire Field
Effect Transistors," Nano Lett., vol. 6, pp. 973-977, 2006.
[6] Y. Jiang, et al., "Nanowire FETs for low power CMOS applications
featuring novel gate-all-around single metal FUSI gates with dual Φm and and VT tune-ability," in IEDM Tech. Dig., 2008, pp. 869-872.
[7] H. Fukutome, et al. "Cost-Effective Ni-Melt-FUSI Boosting 32-nm Node LSTP Transistors," in Symp. VLSI Tech., 2008, pp. 150-151.
[8] J. A. Kittl, et al., "Phase effects and short gate length devise implementation of Ni fully silicided (FUSI) gates," Microelectron. Eng.,
vol. 83, no. 11-12 pp. 2117-2121, Nov. 2006.
[9] T.-Y. Liow, et al., "Strained N-channel FinFETs with High-Stress
Nickel Silicide-Carbon Contacts and Integration with FUSI Metal Gate Technology," in SSDM, 2007, pp. 872-873.
[10] J. Kedzierski, et al., "Fabrication of metal gated FinFETs through
complete gate silicidation with Ni," IEEE Trans. Electron Devices, vol.
51, no. 12, pp. 2115-2120, Dec. 2004.
[11] S.-J. Choi, et al., "Dopant-Segregated Schottky Source/Drain FinFET
With a NiSi FUSI Gate and Reduced Leakage Current," IEEE TED, to
be published.
[12] F. F. Zhao, et al., "Thermal stability study of NiSi and NiSi2 thin films,"
Microelec. Eng., vol. 71, no. 1, pp. 104-111, Jan. 2004.
[13] H. Iwai, T. Ohguro, and S. Ohmi, "NiSi Salicide technology for scaled CMOS,"
Microelec. Eng., vol. 60, no. 1-2, pp. 157-169, Jan. 2002.
[1] S. Bangsaruntip, et al., "High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling", in IEDM Tech. Dig., 2009, pp. 297-300.
[2] N. Singh, et al., "Si, SiGe nanowire devices by top-down technology
and their applications," IEEE TED, vol. 55, no. 11, pp. 3107-3118, Nov.
2008.
[3] S. D. Suk, et al., "High Performance 5nm radius Twin Silicon Nanowire
MOSFET (TSNWFET) : Fabrication on Bulk Si Wafer, Characteristics,
and Reliability," in IEDM Tech. Dig., 2005, pp. 717-720.
[4] B. Yang, et al., "Vertical silicon-nanowire formation and gate-all around
MOSFET," IEEE EDL, vol. 29, no. 7, pp. 791-794, Jul. 2008.
[5] J. Goldberger, et al., "Silicon Vertically Integrated Nanowire Field
Effect Transistors," Nano Lett., vol. 6, pp. 973-977, 2006.
[6] Y. Jiang, et al., "Nanowire FETs for low power CMOS applications
featuring novel gate-all-around single metal FUSI gates with dual Φm and and VT tune-ability," in IEDM Tech. Dig., 2008, pp. 869-872.
[7] H. Fukutome, et al. "Cost-Effective Ni-Melt-FUSI Boosting 32-nm Node LSTP Transistors," in Symp. VLSI Tech., 2008, pp. 150-151.
[8] J. A. Kittl, et al., "Phase effects and short gate length devise implementation of Ni fully silicided (FUSI) gates," Microelectron. Eng.,
vol. 83, no. 11-12 pp. 2117-2121, Nov. 2006.
[9] T.-Y. Liow, et al., "Strained N-channel FinFETs with High-Stress
Nickel Silicide-Carbon Contacts and Integration with FUSI Metal Gate Technology," in SSDM, 2007, pp. 872-873.
[10] J. Kedzierski, et al., "Fabrication of metal gated FinFETs through
complete gate silicidation with Ni," IEEE Trans. Electron Devices, vol.
51, no. 12, pp. 2115-2120, Dec. 2004.
[11] S.-J. Choi, et al., "Dopant-Segregated Schottky Source/Drain FinFET
With a NiSi FUSI Gate and Reduced Leakage Current," IEEE TED, to
be published.
[12] F. F. Zhao, et al., "Thermal stability study of NiSi and NiSi2 thin films,"
Microelec. Eng., vol. 71, no. 1, pp. 104-111, Jan. 2004.
[13] H. Iwai, T. Ohguro, and S. Ohmi, "NiSi Salicide technology for scaled CMOS,"
Microelec. Eng., vol. 60, no. 1-2, pp. 157-169, Jan. 2002.
@article{"International Journal of Electrical, Electronic and Communication Sciences:63026", author = "Z. X. Chen and N. Singh and D.-L. Kwong", title = "Vertical Silicon Nanowire MOSFET With A Fully-Silicided (FUSI) NiSi2 Gate", abstract = "This paper presents a vertical silicon nanowire n- MOSFET integrated with a CMOS-compatible fully-silicided (FUSI) NiSi2 gate. Devices with nanowire diameter of 50nm show good electrical performance (SS < 70mV/dec, DIBL < 30mV/V, Ion/Ioff > 107). Most significantly, threshold voltage tunability of about 0.2V is shown. Although threshold voltage remains low for the 50nm diameter device, it is expected to become more positive as nanowire diameter reduces.
", keywords = "NiSi , fully-silicided (FUSI) gate, vertical siliconnanowire (SiNW), CMOS compatible.", volume = "5", number = "9", pages = "1276-3", }
