Abstract: This paper presents a new compact analytical model of
the gate leakage current in high-k based nano scale MOSFET by
assuming a two-step inelastic trap-assisted tunneling (ITAT) process
as the conduction mechanism. This model is based on an inelastic
trap-assisted tunneling (ITAT) mechanism combined with a semiempirical
gate leakage current formulation in the BSIM 4 model. The
gate tunneling currents have been calculated as a function of gate
voltage for different gate dielectrics structures such as HfO2, Al2O3
and Si3N4 with EOT (equivalent oxide thickness) of 1.0 nm. The
proposed model is compared and contrasted with santaurus
simulation results to verify the accuracy of the model and excellent
agreement is found between the analytical and simulated data. It is
observed that proposed analytical model is suitable for different highk
gate dielectrics simply by adjusting two fitting parameters. It was
also shown that gate leakages reduced with the introduction of high-k
gate dielectric in place of SiO2.
Abstract: Aggressive scaling of MOS devices requires use of ultra-thin gate oxides to maintain a reasonable short channel effect and to take the advantage of higher density, high speed, lower cost etc. Such thin oxides give rise to high electric fields, resulting in considerable gate tunneling current through gate oxide in nano regime. Consequently, accurate analysis of gate tunneling current is very important especially in context of low power application. In this paper, a simple and efficient analytical model has been developed for channel and source/drain overlap region gate tunneling current through ultra thin gate oxide n-channel MOSFET with inevitable deep submicron effect (DSME).The results obtained have been verified with simulated and reported experimental results for the purpose of validation. It is shown that the calculated tunnel current is well fitted to the measured one over the entire oxide thickness range. The proposed model is suitable enough to be used in circuit simulator due to its simplicity. It is observed that neglecting deep sub-micron effect may lead to large error in the calculated gate tunneling current. It is found that temperature has almost negligible effect on gate tunneling current. It is also reported that gate tunneling current reduces with the increase of gate oxide thickness. The impact of source/drain overlap length is also assessed on gate tunneling current.
Abstract: In this paper, for the first time, a two-dimensional
(2D) analytical drain current model for sub-100 nm multi-layered
gate material engineered trapezoidal recessed channel (MLGMETRC)
MOSFET: a novel design is presented and investigated using
ATLAS and DEVEDIT device simulators, to mitigate the large gate
leakages and increased standby power consumption that arise due to
continued scaling of SiO2-based gate dielectrics. The twodimensional
(2D) analytical model based on solution of Poisson-s
equation in cylindrical coordinates, utilizing the cylindrical
approximation, has been developed which evaluate the surface
potential, electric field, drain current, switching metric: ION/IOFF
ratio and transconductance for the proposed design. A good
agreement between the model predictions and device simulation
results is obtained, verifying the accuracy of the proposed analytical
model.
Abstract: In this paper we investigate the electrical
characteristics of a new structure of gate all around strained silicon
nanowire field effect transistors (FETs) with dual dielectrics by
changing the radius (RSiGe) of silicon-germanium (SiGe) wire and
gate dielectric. Indeed the effect of high-κ dielectric on Field Induced
Barrier Lowering (FIBL) has been studied. Due to the higher electron
mobility in tensile strained silicon, the n-type FETs with strained
silicon channel have better drain current compare with the pure Si
one. In this structure gate dielectric divided in two parts, we have
used high-κ dielectric near the source and low-κ dielectric near the
drain to reduce the short channel effects. By this structure short
channel effects such as FIBL will be reduced indeed by increasing
the RSiGe, ID-VD characteristics will be improved. The leakage
current and transfer characteristics, the threshold-voltage (Vt), the
drain induced barrier height lowering (DIBL), are estimated with
respect to, gate bias (VG), RSiGe and different gate dielectrics. For
short channel effects, such as DIBL, gate all around strained silicon
nanowire FET have similar characteristics with the pure Si one while
dual dielectrics can improve short channel effects in this structure.