Abstract: In this paper, the design of wide-swing constant transconductance (gm) bias circuit that generates bias voltage for low-noise amplifier (LNA) circuit design by using an off-chip resistor is demonstrated. The overall transconductance (Gm) generated by the constant gm bias circuit is important to maintain the overall gain and noise figure of the LNA circuit. Therefore, investigation is performed to study the variation in Gm with process, temperature and supply voltage (PVT). Temperature and supply voltage are swept from -10 °C to 85 °C and 1.425 V to 1.575 V respectively, while the process conditions are also varied to the extreme and the gm variation is eventually concluded at between -3 % to 7 %. With the slight variation in the gm value, through simulation, at worst condition of state SS, we are able to attain a conversion gain (S21) variation of -3.10 % and a noise figure (NF) variation of 18.71 %. The whole constant gm circuit draws approximately 100 µA from a 1.5V supply and is designed based on 0.13 µm CMOS process.
Abstract: This paper presents the design and implementation of a fully integrated Capacitance-to-Voltage Converter (CVC) as the analog front-end for magnetometer interface IC. The application demands very low power solution operating in the frequency of around 20 KHz. The design adapts low power architecture to create low noise electronic interface for Capacitive Micro-machined Lorentz force magnetometer sensor. Using a 0.18-μm CMOS process, simulation results of this interface IC show that the proposed CVC can provide 33 dB closed loop gain, 20 nV/√Hz input referred noise at 20 KHz, while consuming 65 μA current from 1.8-V supply.
Abstract: This paper describes the design of new method of
propagation delay measurement in micro and nanostructures during
characterization of ASIC standard library cell. Providing more
accuracy timing information about library cell to the design team we
can improve a quality of timing analysis inside of ASIC design flow
process. Also, this information could be very useful for semiconductor
foundry team to make correction in technology process. By
comparison of the propagation delay in the CMOS element and result
of analog SPICE simulation. It was implemented as digital IP core for
semiconductor manufacturing process. Specialized method helps to
observe the propagation time delay in one element of the standard-cell
library with up-to picoseconds accuracy and less. Thus, the special
useful solutions for VLSI schematic to parameters extraction, basic
cell layout verification, design simulation and verification are
announced.
Abstract: This paper presents a resonant-based read-out circuit for capacitive pressure sensors. The proposed read-out circuit consists of an LC oscillator and a counter. The circuit detects the capacitance changes of a capacitive pressure sensor by means of frequency shifts from its nominal operation frequency. The proposed circuit is designed in 0.18 m CMOS with an estimated power consumption of 43.1mW. Simulation results show that the circuit has a capacitive resolution of 8.06kHz/fF, which enables it for high resolution pressure detection.
Abstract: A high-linearity and high-speed current-mode sampleand-
hold circuit is designed and simulated using a 0.25μm CMOS
technology. This circuit design is based on low voltage and it utilizes
a fully differential circuit. Due to the use of only two switches the
switch related noise has been reduced. Signal - dependent -error is
completely eliminated by a new zero voltage switching technique.
The circuit has a linearity error equal to ±0.05μa, i.e. 12-bit
accuracy with a ±160 μa differential output - input signal frequency
of 5MHZ, and sampling frequency of 100 MHZ. Third
harmonic is equal to –78dB.
Abstract: A new design approach for three-stage operational
amplifiers (op-amps) is proposed. It allows to actually implement a
symmetrical push-pull class-AB amplifier output stage for wellestablished
three-stage amplifiers using a feedforward
transconductance stage. Compared with the conventional design
practice, the proposed approach leads to a significant
improvement of the symmetry between the positive and the
negative op-amp step response, resulting in similar values of the
positive/negative settling time. The new approach proves to be very
useful in order to fully exploit the potentiality allowed by the op-amp
in terms of speed performances. Design examples in a commercial
0.35-μm CMOS prove the effectiveness of theproposed strategy.
Abstract: In this paper, some experiments of liquid dispersion flow driven by explosion in vertical plane were carried out using a liquid explosive dispersion device with film cylindrical constraints. The separated time series describing the breakup shape and dispersion process of liquid were recorded with high speed CMOS camera. The experimental results were analyzed and some essential characteristics of liquid dispersing flow are presented.
Abstract: This paper presents the design and layout of a two stage, high speed operational amplifiers using standard 0.35um CMOS technology. The design procedure involves designing the bias circuit, the differential input pair, and the gain stage using CAD tools. Both schematic and layout of the operational amplifier along with the comparison in the results of the two has been presented. The operational amplifier designed, has a gain of 93.51db at low frequencies. It has a gain bandwidth product of 55.07MHz, phase margin of 51.9º and a slew rate of 22v/us for a load of capacitor of 10pF.
Abstract: To help overcome limits to the density of conventional SRAMs and leakage current of SRAM cell in nanoscaled CMOS technology, we have developed a four-transistor SRAM cell. The newly developed CMOS four-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 19% smaller than a conventional six-transistor cell using same design rules. Also the leakage current of new cell is 60% smaller than a conventional sixtransistor SRAM cell. Simulation result in 65nm CMOS technology shows new cell has correct operation during read/write operation and idle mode.
Abstract: In this paper we introduce an ultra low power CMOS
LC oscillator and analyze a method to design a low power low phase
noise complementary CMOS LC oscillator. A 1.8GHz oscillator is
designed based on this analysis. The circuit has power supply equal
to 1.1 V and dissipates 0.17 mW power. The oscillator is also
optimized for low phase noise behavior. The oscillator phase noise is
-126.2 dBc/Hz and -144.4 dBc/Hz at 1 MHz and 8 MHz offset
respectively.
Abstract: This paper presents a SCR-based ESD protection devices for I/O clamp and power rail clamp, respectably. These devices have a low trigger voltage and high holding voltage characteristics than conventional SCR device. These devices are fabricated by using 0.35um BCD (Bipolar-CMOS-DMOS) processes. These devices were validated using a TLP system. From the experimental results, the device for I/O ESD clamp has a trigger voltage of 5.8V. Also, the device for power rail ESD clamp has a holding voltage of 7.7V.
Abstract: This paper presents a new method for read out of the piezoresistive accelerometer sensors. The circuit works based on Instrumentation amplifier and it is useful for reducing offset In Wheatstone Bridge. The obtained gain is 645 with 1μv/°c Equivalent drift and 1.58mw power consumption. A Schmitt trigger and multiplexer circuit control output node. a high speed counter is designed in this work .the proposed circuit is designed and simulated In 0.18μm CMOS technology with 1.8v power supply.
Abstract: This work is a proposed model of CMOS for which
the algorithm has been created and then the performance evaluation
of this proposition has been done. In this context, another commonly
used model called ZSTT (Zero Switching Time Transient) model is
chosen to compare all the vital features and the results for the
Proposed Equivalent CMOS are promising. In the end, the excerpts
of the created algorithm are also included
Abstract: Photo-BJMOSFET (Bipolar Junction Metal-Oxide-
Semiconductor Field Effect Transistor) fabricated on SOI film was proposed. ITO film is adopted in the device as gate electrode to reduce
light absorption. Depletion region but not inversion region is formed
in film by applying gate voltage (but low reverse voltage) to achieve
high photo-to-dark-current ratio. Comparisons of photoelectriccharacteristics
executed among VGK=0V, 0.3V, 0.6V, 0.9V and 1.0V
(reverse voltage VAK is equal to 1.0V for total area of 10×10μm2). The
results indicate that the greatest improvement in photo-to-dark-current
ratio is achieved up to 2.38 at VGK=0.6V. In addition,
photo-BJMOSFET is compatible with CMOS integration due to big
input resistance
Abstract: We present an integration approach of a CMOS biosensor into a polymer based microfluidic environment suitable for mass production. It consists of a wafer-level-package for the silicon die and laser bonding process promoted by an intermediate hot melt foil to attach the sensor package to the microfluidic chip, without the need for dispensing of glues or underfiller. A very good condition of the sensing area was obtained after introducing a protection layer during packaging. A microfluidic flow cell was fabricated and shown to withstand pressures up to Δp = 780 kPa without leakage. The employed biosensors were electrically characterized in a dry environment.
Abstract: Although the field of parametric Pattern Recognition (PR) has been thoroughly studied for over five decades, the use of the Order Statistics (OS) of the distributions to achieve this has not been reported. The pioneering work on using OS for classification was presented in [1] for the Uniform distribution, where it was shown that optimal PR can be achieved in a counter-intuitive manner, diametrically opposed to the Bayesian paradigm, i.e., by comparing the testing sample to a few samples distant from the mean. This must be contrasted with the Bayesian paradigm in which, if we are allowed to compare the testing sample with only a single point in the feature space from each class, the optimal strategy would be to achieve this based on the (Mahalanobis) distance from the corresponding central points, for example, the means. In [2], we showed that the results could be extended for a few symmetric distributions within the exponential family. In this paper, we attempt to extend these results significantly by considering asymmetric distributions within the exponential family, for some of which even the closed form expressions of the cumulative distribution functions are not available. These distributions include the Rayleigh, Gamma and certain Beta distributions. As in [1] and [2], the new scheme, referred to as Classification by Moments of Order Statistics (CMOS), attains an accuracy very close to the optimal Bayes’ bound, as has been shown both theoretically and by rigorous experimental testing.
Abstract: This paper proposes a low-voltage and low-power
fully integrated digitally tuned continuous-time channel selection
filter for WiMAX applications. A 5th-order elliptic low-pass filter is
realized in a Gm-C topology. The bandwidth of the fully differential
filter is reconfigurable from 2.5MHz to 20MHz (8x) for different
requirements in WiMAX applications. The filter is simulated in a
standard 90nm CMOS process. Simulation results show the THD
(@Vout =100mVpp) is less than -66dB. The in-band ripple of the
filter is about 0.15dB. The filter consumes 1.5mW from a supply
voltage of 0.9V.
Abstract: A 1.2 V, 0.61 mA bias current, low noise amplifier
(LNA) suitable for low-power applications in the 2.4 GHz band is
presented. Circuit has been implemented, laid out and simulated using
a UMC 130 nm RF-CMOS process. The amplifier provides a 13.3 dB
power gain a noise figure NF< 2.28 dB and a 1-dB compression point
of -15.69 dBm, while dissipating 0.74 mW. Such performance make
this design suitable for wireless sensor networks applications such as
ZigBee.
Abstract: This paper presents a vertical silicon nanowire n- MOSFET integrated with a CMOS-compatible fully-silicided (FUSI) NiSi2 gate. Devices with nanowire diameter of 50nm show good electrical performance (SS < 70mV/dec, DIBL < 30mV/V, Ion/Ioff > 107). Most significantly, threshold voltage tunability of about 0.2V is shown. Although threshold voltage remains low for the 50nm diameter device, it is expected to become more positive as nanowire diameter reduces.
Abstract: A fast settling multipath CMOS OTA for high speed
switched capacitor applications is presented here. With the basic
topology similar to folded-cascode, bandwidth and DC gain of the
OTA are enhanced by adding extra paths for signal from input to
output. Designed circuit is simulated with HSPICE using level 49
parameters (BSIM 3v3) in 0.35mm standard CMOS technology. DC
gain achieved is 56.7dB and Unity Gain Bandwidth (UGB) obtained
is 1.15GHz. These results confirm that adding extra paths for signal
can improve DC gain and UGB of folded-cascode significantly.