Phase Error Accumulation Methodology for On-Chip Cell Characterization
This paper describes the design of new method of
propagation delay measurement in micro and nanostructures during
characterization of ASIC standard library cell. Providing more
accuracy timing information about library cell to the design team we
can improve a quality of timing analysis inside of ASIC design flow
process. Also, this information could be very useful for semiconductor
foundry team to make correction in technology process. By
comparison of the propagation delay in the CMOS element and result
of analog SPICE simulation. It was implemented as digital IP core for
semiconductor manufacturing process. Specialized method helps to
observe the propagation time delay in one element of the standard-cell
library with up-to picoseconds accuracy and less. Thus, the special
useful solutions for VLSI schematic to parameters extraction, basic
cell layout verification, design simulation and verification are
announced.
[1] S. Maggioni, A. Veggetti, A. Bogliolo, L. Croce, "Random sampling for
on-chip characterization of standard cell propagation delay", in
Proceedings of the Fourth International Symposium on Quality Electronic
Design, 24-26 March 2003, pp. 41- 45.
[2] Churayev S.O., Matkarimov B.T., Paltashev T.T., "On-chip
Measurements of Standard-Cell Propagation Delay", Proceedings of
IEEE East-West Design & Test Symposium (EWDTS-09), September
18-21 2009, Moscow. 2009. pp. 93-95.
[3] S. K. Thompson, Sampling, 2nd Edition, Wiley, 2002.
[4] Extrapolation Methods. Theory and Practice by C. Brezinski and M.
Redivo Zaglia, North-Holland, 1991.
[1] S. Maggioni, A. Veggetti, A. Bogliolo, L. Croce, "Random sampling for
on-chip characterization of standard cell propagation delay", in
Proceedings of the Fourth International Symposium on Quality Electronic
Design, 24-26 March 2003, pp. 41- 45.
[2] Churayev S.O., Matkarimov B.T., Paltashev T.T., "On-chip
Measurements of Standard-Cell Propagation Delay", Proceedings of
IEEE East-West Design & Test Symposium (EWDTS-09), September
18-21 2009, Moscow. 2009. pp. 93-95.
[3] S. K. Thompson, Sampling, 2nd Edition, Wiley, 2002.
[4] Extrapolation Methods. Theory and Practice by C. Brezinski and M.
Redivo Zaglia, North-Holland, 1991.
@article{"International Journal of Electrical, Electronic and Communication Sciences:64797", author = "Chang Soo Kang and In Ho Im and Sergey Churayev and Timour Paltashev", title = "Phase Error Accumulation Methodology for On-Chip Cell Characterization", abstract = "This paper describes the design of new method of
propagation delay measurement in micro and nanostructures during
characterization of ASIC standard library cell. Providing more
accuracy timing information about library cell to the design team we
can improve a quality of timing analysis inside of ASIC design flow
process. Also, this information could be very useful for semiconductor
foundry team to make correction in technology process. By
comparison of the propagation delay in the CMOS element and result
of analog SPICE simulation. It was implemented as digital IP core for
semiconductor manufacturing process. Specialized method helps to
observe the propagation time delay in one element of the standard-cell
library with up-to picoseconds accuracy and less. Thus, the special
useful solutions for VLSI schematic to parameters extraction, basic
cell layout verification, design simulation and verification are
announced.", keywords = "phase error accumulation methodology, gatepropagation delay, Processor Testing, MEMS Testing", volume = "5", number = "7", pages = "885-4", }