Abstract: Insulators are one of the most significant equipment in power system. The insulators’ operation may affect the power flow, line loss and reliability. The electrical parameters that influence the performance of insulator are surface leakage current, corona and dry band arcing. Electric field stresses on the insulator surface will degrade the insulating properties and lead to puncture. Electric filed stresses can be analyzed by numerical methods and experimental evaluation. As per economic aspects, evaluation by numerical methods are best. In outdoor insulation, a hydrophobic surface can facilitate to prevent water film formation on the insulation surface, which is decisive for diminishing leakage currents and partial discharge (PD) under heavy polluted environments and harsh weather conditions. Polymer materials like silicone rubber have an outstanding hydrophobic property among general insulation materials. In this paper, electrical field intensity of 220 kV porcelain and polymer double tension insulator strings at critical regions are analyzed and compared by using Finite Element Method. Hydrophobic conditions of polymer insulator with equal and unequal water molecule conditions are verified by using finite element method.
Abstract: Leakage current monitoring for high voltage transmission line insulators is of interest as a performance indicator. Presently, to the best of our knowledge, there is no commercially available, clamp-on type, non-intrusive device for measuring leakage current on energised high voltage direct current (HVDC) transmission line insulators. The South African power utility, Eskom, is investigating the development of such a hand-held sensor for two important applications; first, for continuous real-time condition monitoring of HVDC line insulators and, second, for use by live line workers to determine if it is safe to work on energised insulators. In this paper, a DC leakage current sensor based on magnetic field sensing techniques is developed. The magnetic field sensor used in the prototype can also detect alternating current up to 5 MHz. The DC leakage current prototype detects the magnetic field associated with the current flowing on the surface of the insulator. Preliminary HVDC leakage current measurements are performed on glass insulators. The results show that the prototype can accurately measure leakage current in the specified current range of 1-200 mA. The influence of external fields from the HVDC line itself on the leakage current measurements is mitigated through a differential magnetometer sensing technique. Thus, the developed sensor can perform measurements on in-service HVDC insulators. The research contributes to the body of knowledge by providing a sensor to measure leakage current on energised HVDC insulators non-intrusively. This sensor can also be used by live line workers to inform them whether or not it is safe to perform maintenance on energized insulators.
Abstract: This paper presents PV system without considering transformer connected to electric grid. This is considered more economic compared to present PV system. The problem that occurs when transformer is not considered appears with a leakage current near capacitor connected to ground. Bipolar Pulse Width Modulation (BPWM) technique along with filter L-C-L configuration in the circuit is modeled to shrink the leakage current in the circuit. The DC/AC inverter is modeled using H-bridge Insulated Gate Bipolar Transistor (IGBT) module which is controlled using proposed Bipolar PWM control technique. To extract maximum power, Maximum Power Point Technique (MPPT) controller is used in this model. Voltage and current regulators are used to determine the reference voltage for the inverter from active and reactive current where reactive current is set to zero. The PLL is modeled to synchronize the measurements. The model is designed with MATLAB Simulation blocks and compared with the methods available in literature survey to show its effectiveness.
Abstract: Fast neutron irradiation using nuclear reactors is an effective method to improve switching loss and short circuit durability of power semiconductor (insulated gate bipolar transistors (IGBT) and insulated gate transistors (IGT), etc.). However, not only fast neutrons but also thermal neutrons, epithermal neutrons and gamma exist in the nuclear reactor. And the electrical properties of the IGBT may be deteriorated by the irradiation of gamma. Gamma irradiation damages are known to be caused by Total Ionizing Dose (TID) effect and Single Event Effect (SEE), Displacement Damage. Especially, the TID effect deteriorated the electrical properties such as leakage current and threshold voltage of a power semiconductor. This work can confirm the effect of the gamma irradiation on the electrical properties of 600 V NPT-IGBT. Irradiation of gamma forms lattice defects in the gate oxide and Si-SiO2 interface of the IGBT. It was confirmed that this lattice defect acts on the center of the trap and affects the threshold voltage, thereby negatively shifted the threshold voltage according to TID. In addition to the change in the carrier mobility, the conductivity modulation decreases in the n-drift region, indicating a negative influence that the forward voltage drop decreases. The turn-off delay time of the device before irradiation was 212 ns. Those of 2.5, 10, 30, 70 and 100 kRad(Si) were 225, 258, 311, 328, and 350 ns, respectively. The gamma irradiation increased the turn-off delay time of the IGBT by approximately 65%, and the switching characteristics deteriorated.
Abstract: In this letter, we demonstrate high-performance AlGaN/GaN planar Schottky barrier diodes (SBDs) on the silicon substrate with field plate structure for increasing breakdown voltage VB. A low turn-on resistance RON (3.55 mΩ-cm2), low reverse leakage current (< 0.1 µA) at -100 V, and high reverse breakdown voltage VB (> 1.1 kV) SBD has been fabricated. A virgin SBD exhibited a breakdown voltage (measured at 1 mA/mm) of 615 V, and with the field plate technology device exhibited a breakdown voltage (measured at 1 mA/mm) of 1525 V (the anode–cathode distance was LAC = 40 µm). Devices without the field plate design exhibit a Baliga’s figure of merit of VB2/ RON = 60.2 MW/cm2, whereas devices with the field plate design show a Baliga’s figure of merit of VB2/ RON = 340.9 MW/cm2 (the anode–cathode distance was LAC = 20 µm).
Abstract: Power dissipation increases exponentially during test mode as compared to normal operation of the circuit. In extreme cases, test power is more than twice the power consumed during normal operation mode. Test vector generation scheme is key component in deciding the power hungriness of a circuit during testing. Test vector count and consequent leakage current are functions of test vector generation scheme. Fault based test vector count optimization has been presented in this work. It helps in reducing test vector count and the leakage current. In the presented scheme, test vectors have been reduced by extracting essential child vectors. The scheme has been tested experimentally using stuck at fault models and results ensure the reduction in test vector count.
Abstract: This paper presents the experimental results of 11 kV
and 33 kV silicon composite insulators under artificial salt and urea
polluted conditions. The tests were carried out under different
seasons like summer, winter, and monsoon. The artificial pollution is
prepared by properly dissolving the salt and urea in the water. The
prepared salt and urea pollutions are sprayed on the insulators and
dried up for sufficiently large time. The process is continued until a
uniform layer is formed on the surface of insulator. For each insulator
rating, four samples were tested. The maximum leakage current and
breakdown voltage were measured. From experimental data,
performance of test specimen is evaluated by comparing breakdown
voltage and leakage current during different seasons when exposed to
salt and urea polluted conditions. From these results the performance
of the insulators can be predicted when they are installed in
industrial, agricultural, and coastal areas. The experimental tests were
carried out in the High Voltage laboratory using two stage cascade
transformer having the rating of 1000 kVA, 500 kV.
Abstract: The photovoltaic (PV) panel with no galvanic
isolation system is well known technique in the world which is
effective and delivers power with enhanced efficiency. The PV
generation presented here is for stand-alone system installed in
remote areas when as the resulting power gets connected to electronic
load installation instead of being tied to the grid. Though very small,
even then transformer-less topology is shown to be with leakage in
pico-ampere range. By using PWM technique PWM, leakage current
in different situations is shown. The results shown in this paper show
how the pico-ampere current is reduced to femto-ampere through use
of inductors and capacitors of suitable values of inductor and
capacitors with the load.
Abstract: As the Silicon oxide scaled down in MOSFET
technology to few nanometers, gate Direct Tunneling (DT) in
Floating gate (FGMOSFET) devices has become a major concern for
analog designers. FGMOSFET has been used in many low-voltage
and low-power applications, however, there is no accurate model that
account for DT gate leakage in nano-scale. This paper studied and
analyzed different simulation models for FGMOSFET using TSMC
90-nm technology. The simulation results for FGMOSFET cascade
current mirror shows the impact of DT on circuit performance in
terms of current and voltage without the need for fabrication. This
works shows the significance of using an accurate model for
FGMOSFET in nan-scale technologies.
Abstract: Most of the PV systems are designed with transformer for safety purpose with galvanic isolation. However, the transformer is big, heavy and expensive. Also, it reduces the overall frequency of the conversion stage. Generally PV inverter with transformer is having efficiency around 92%–94% only. To overcome these problems, transformerless PV system is introduced. It is smaller, lighter, cheaper and higher in efficiency. However, dangerous leakage current will flow between PV array and the grid due to the stray capacitance. There are different types of configurations available for transformerless inverters like H5, H6, HERIC, oH5, and Dual paralleled buck inverter. But each configuration is suffering from its own disadvantages like high conduction losses, shoot-through issues of switches, dead-time requirements at zero crossing instants of grid voltage to avoid grid shoot-through faults and MOSFET reverse recovery issues. The main objective of the proposed transformerless inverter is to address two key issues: One key issue for a transformerless inverter is that it is necessary to achieve high efficiency compared to other existing inverter topologies. Another key issue is that the inverter configuration should not have any shoot-through issues for higher reliability.
Abstract: CNFET has emerged as an alternative material to
silicon for high performance, high stability and low power SRAM
design in recent years. SRAM functions as cache memory in
computers and many portable devices. In this paper, a new SRAM
cell design based on CNFET technology is proposed. The proposed
SRAM cell design for CNFET is compared with SRAM cell designs
implemented with the conventional CMOS and FinFET in terms of
speed, power consumption, stability, and leakage current. The
HSPICE simulation and analysis show that the dynamic power
consumption of the proposed 8T CNFET SRAM cell’s is reduced
about 48% and the SNM is widened up to 56% compared to the
conventional CMOS SRAM structure at the expense of 2% leakage
power and 3% write delay increase.
Abstract: Speed, power consumption and area, are some of the most important factors of concern in modern day memory design. As we move towards Deep Sub-Micron Technologies, the problems of leakage current, noise and cell stability due to physical parameter variation becomes more pronounced. In this paper we have designed an 8T Read Decoupled Dual Port SRAM Cell with Dual Threshold Voltage and characterized it in terms of read and write delay, read and write noise margins, Data Retention Voltage and Leakage Current. Read Decoupling improves the Read Noise Margin and static power dissipation is reduced by using Dual-Vt transistors. The results obtained are compared with existing 6T, 8T, 9T SRAM Cells, which shows the superiority of the proposed design. The Cell is designed and simulated in TSPICE using 90nm CMOS process.
Abstract: Minimizations of power dissipation, chip area with higher circuit performance are the necessary and key parameters in deep submicron regime. The leakage current increases sharply in deep submicron regime and directly affected the power dissipation of the logic circuits. In deep submicron region the power dissipation as well as high performance is the crucial concern since increasing importance of portable systems. Number of leakage reduction techniques employed to reduce the leakage current in deep submicron region but they have some trade-off to control the leakage current. ONOFIC approach gives an excellent agreement between power dissipation and propagation delay for designing the efficient CMOS logic circuits. In this article ONOFIC approach is compared with LECTOR technique and output results show that ONOFIC approach significantly reduces the power dissipation and enhance the speed of the logic circuits. The lower power delay product is the big outcome of this approach and makes it an influential leakage reduction technique.
Abstract: Power dissipation due to leakage current in the digital circuits is a biggest factor which is considered specially while designing nanoscale circuits. This paper is exploring the ideas of reducing leakage current in static CMOS circuits by stacking the transistors in increasing numbers. Clearly it means that the stacking of OFF transistors in large numbers result a significant reduction in power dissipation. Increase in source voltage of NMOS transistor minimizes the leakage current. Thus stacking technique makes circuit with minimum power dissipation losses due to leakage current. Also some of digital circuits such as full adder, D flip flop and 6T SRAM have been simulated in this paper, with the application of reduction technique on ‘cadence virtuoso tool’ using specter at 45nm technology with supply voltage 0.7V.
Abstract: This paper presents a new compact analytical model of
the gate leakage current in high-k based nano scale MOSFET by
assuming a two-step inelastic trap-assisted tunneling (ITAT) process
as the conduction mechanism. This model is based on an inelastic
trap-assisted tunneling (ITAT) mechanism combined with a semiempirical
gate leakage current formulation in the BSIM 4 model. The
gate tunneling currents have been calculated as a function of gate
voltage for different gate dielectrics structures such as HfO2, Al2O3
and Si3N4 with EOT (equivalent oxide thickness) of 1.0 nm. The
proposed model is compared and contrasted with santaurus
simulation results to verify the accuracy of the model and excellent
agreement is found between the analytical and simulated data. It is
observed that proposed analytical model is suitable for different highk
gate dielectrics simply by adjusting two fitting parameters. It was
also shown that gate leakages reduced with the introduction of high-k
gate dielectric in place of SiO2.
Abstract: To help overcome limits to the density of conventional SRAMs and leakage current of SRAM cell in nanoscaled CMOS technology, we have developed a four-transistor SRAM cell. The newly developed CMOS four-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 19% smaller than a conventional six-transistor cell using same design rules. Also the leakage current of new cell is 60% smaller than a conventional sixtransistor SRAM cell. Simulation result in 65nm CMOS technology shows new cell has correct operation during read/write operation and idle mode.
Abstract: This work aims to reduce the read power consumption
as well as to enhance the stability of the SRAM cell during the read
operation. A new 10-transisor cell is proposed with a new read
scheme to minimize the power consumption within the memory core.
It has separate read and write ports, thus cell read stability is
significantly improved. A 16Kb SRAM macro operating at 1V
supply voltage is demonstrated in 65 nm CMOS process. Its read
power consumption is reduced to 24% of the conventional design.
The new cell also has lower leakage current due to its special bit-line
pre-charge scheme. As a result, it is suitable for low-power mobile
applications where power supply is restricted by the battery.
Abstract: Laboratory classes in Electrical Engineering are often hampered by safety issues, as students have to work on high voltage lines. One solution is to make use of virtual laboratory simulations, to help students understand the concepts taught in their coursework. In this context, we have conceived and implemented virtual lab experiments in connection with the study of earthing arrangements. In this work, software was developed, which aid student in understanding the working of a residual current device (RCD) in a TT earthing system. Various parameters, such as the earthing resistances, leakage currents and harmonics were included for a TT system with RCD connection.
Abstract: In this paper, FinFET devices are analyzed with
emphasis on sub-threshold leakage current control. This is achieved
through proper biasing of the back gate, and through the use of
asymmetric work functions for the four terminal FinFET devices. We
are also examining different configurations of multiplexers and XOR
gates using transistors of symmetric and asymmetric work functions.
Based on extensive characterization data for MUX circuits, our
proposed configuration using symmetric devices lead to leakage
current and delay improvements of 65% and 47% respectively
compared to results in the literature. For XOR gates, a 90%
improvement in the average leakage current is achieved by using
asymmetric devices. All simulations are based on a 25nm FinFET
technology using the University of Florida UFDG model.
Abstract: This paper propose a new circuit design which
monitor total leakage current during standby mode and generates the
optimal reverse body bias voltage, by using the adaptive body bias
(ABB) technique to compensate die-to-die parameter variations.
Design details of power monitor are examined using simulation
framework in 65nm and 32nm BTPM model CMOS process.
Experimental results show the overhead of proposed circuit in terms
of its power consumption is about 10 μW for 32nm technology and
about 12 μW for 65nm technology at the same power supply voltage
as the core power supply. Moreover the results show that our
proposed circuit design is not far sensitive to the temperature
variations and also process variations. Besides, uses the simple
blocks which offer good sensitivity, high speed, the continuously
feedback loop.