Electrical Characteristics of SCR - based ESD Device for I/O and Power Rail Clamp in 0.35um Process
This paper presents a SCR-based ESD protection devices for I/O clamp and power rail clamp, respectably. These devices have a low trigger voltage and high holding voltage characteristics than conventional SCR device. These devices are fabricated by using 0.35um BCD (Bipolar-CMOS-DMOS) processes. These devices were validated using a TLP system. From the experimental results, the device for I/O ESD clamp has a trigger voltage of 5.8V. Also, the device for power rail ESD clamp has a holding voltage of 7.7V.
[1] Huang, et al.., "ESD protection design for advanced CMOS," in Proc.
SPIE, 2001, pp. 123-131.
[2] R.G Wagner, J. Soden and C.F. Hawkins, "Extend and cost of EOS/ESD
Damage in an IC Manufacturing Process," in Proc. of the 15th EOS/ESD
Symp.,2005, 1993, pp. 49-55.
[3] M.D. Ker and C.H. Chuang, "ESD Implantations in 0.18um Salicided
CMOS Technology for On-Chip ESD Protection with Layout
Consideration", Int. Symp. Physical and Failure Analysis of Integrated
Circuits, 2001, pp. 85-90.
[4] C. Russ, M. Mergens, J. Armer, P. Jozwiak, G. Kolluri, L. Avery, and
K.Verhaege, "GGSCRs: GGNMOS triggered silicon controlled rectifiers
for ESD protection in deep submicron CMOS processes," in Proc.
EOS/ESD Symp., 2001, pp. 22-31.
[5] M.-D. Ker and K.-C. Hsu, "Overview of on-chip electrostatic discharge
protection design with SCR-based devices in CMOS integrated circuits,"
IEEE Tran. Device Mater. Reliab. vol. 5, no. 2, Jun 2005, pp. 235-249.
[6] P.-Y. Tan, M. Indrajit, P.-H. Li, and S. H. Voldman, " RC-triggered PNP
and NPN simultaneously switched silicon controlled rectifier ESD
networks for sub-0.18╬╝m technology," in Proc. of IEEE Int. Symp. On
Physical and Failure Analysis of Integrated Circuits,2005, pp. 71-75.
[7] V. Vashchenko, A. Concannon, M. ter Beek, and P. Hopper, "High
holding voltage cascaded LVTSCR structures for 5.5-V tolerant ESD
protection clamps," IEEE Trans. Devices Mater. Rel., vol. 4, 2004, pp.
273-280.
[8] O. Semenov, et al, "ESD Protection Device and Circuit Design for
Advanced CMOS Technologies," Springer. 2008.
[9] J. Barth, Koen Verhaege, Leo G. Henry, and J. Richner, "TLP Calibration,
Correlation, Standards, and New Techniques," Proc. EOS/ESD Symp.,
2000, pp. 85-96.
[10] W. Stadler, X. Guggenmos, P. Egger, H. Gieser and C. Musshoff, "Does
the TLP Failure Current obtained by Transmission Line Pulsing always
correlate to Human body model tests," Proc. EOS/ESD Symp, 1997, pp.
336-372.
[11] G. Notermans, P. de Jong and F. Kuper, Pitfalls, "when correlating TLP,
HBM and MM testing", Proc. EOS/ESD Symp, 1998, pp 170-176
[1] Huang, et al.., "ESD protection design for advanced CMOS," in Proc.
SPIE, 2001, pp. 123-131.
[2] R.G Wagner, J. Soden and C.F. Hawkins, "Extend and cost of EOS/ESD
Damage in an IC Manufacturing Process," in Proc. of the 15th EOS/ESD
Symp.,2005, 1993, pp. 49-55.
[3] M.D. Ker and C.H. Chuang, "ESD Implantations in 0.18um Salicided
CMOS Technology for On-Chip ESD Protection with Layout
Consideration", Int. Symp. Physical and Failure Analysis of Integrated
Circuits, 2001, pp. 85-90.
[4] C. Russ, M. Mergens, J. Armer, P. Jozwiak, G. Kolluri, L. Avery, and
K.Verhaege, "GGSCRs: GGNMOS triggered silicon controlled rectifiers
for ESD protection in deep submicron CMOS processes," in Proc.
EOS/ESD Symp., 2001, pp. 22-31.
[5] M.-D. Ker and K.-C. Hsu, "Overview of on-chip electrostatic discharge
protection design with SCR-based devices in CMOS integrated circuits,"
IEEE Tran. Device Mater. Reliab. vol. 5, no. 2, Jun 2005, pp. 235-249.
[6] P.-Y. Tan, M. Indrajit, P.-H. Li, and S. H. Voldman, " RC-triggered PNP
and NPN simultaneously switched silicon controlled rectifier ESD
networks for sub-0.18╬╝m technology," in Proc. of IEEE Int. Symp. On
Physical and Failure Analysis of Integrated Circuits,2005, pp. 71-75.
[7] V. Vashchenko, A. Concannon, M. ter Beek, and P. Hopper, "High
holding voltage cascaded LVTSCR structures for 5.5-V tolerant ESD
protection clamps," IEEE Trans. Devices Mater. Rel., vol. 4, 2004, pp.
273-280.
[8] O. Semenov, et al, "ESD Protection Device and Circuit Design for
Advanced CMOS Technologies," Springer. 2008.
[9] J. Barth, Koen Verhaege, Leo G. Henry, and J. Richner, "TLP Calibration,
Correlation, Standards, and New Techniques," Proc. EOS/ESD Symp.,
2000, pp. 85-96.
[10] W. Stadler, X. Guggenmos, P. Egger, H. Gieser and C. Musshoff, "Does
the TLP Failure Current obtained by Transmission Line Pulsing always
correlate to Human body model tests," Proc. EOS/ESD Symp, 1997, pp.
336-372.
[11] G. Notermans, P. de Jong and F. Kuper, Pitfalls, "when correlating TLP,
HBM and MM testing", Proc. EOS/ESD Symp, 1998, pp 170-176
@article{"International Journal of Electrical, Electronic and Communication Sciences:64201", author = "Yong Seo Koo and Dong Su Kim and Byung Seok Lee and Won Suk Park and Bo Bea Song", title = "Electrical Characteristics of SCR - based ESD Device for I/O and Power Rail Clamp in 0.35um Process", abstract = "This paper presents a SCR-based ESD protection devices for I/O clamp and power rail clamp, respectably. These devices have a low trigger voltage and high holding voltage characteristics than conventional SCR device. These devices are fabricated by using 0.35um BCD (Bipolar-CMOS-DMOS) processes. These devices were validated using a TLP system. From the experimental results, the device for I/O ESD clamp has a trigger voltage of 5.8V. Also, the device for power rail ESD clamp has a holding voltage of 7.7V.
", keywords = "ESD (Electro-Static Discharge), ESD protection
device, SCR (Silicon Controlled Rectifier), Latch-up", volume = "6", number = "7", pages = "703-4", }
