Abstract: This paper describes a low-power second-order filter
for a continuous-time chopper stabilized capacitive sensor interface,
integrated with a fully differential post-CMOS surface-micromachined
MEMS pressure sensor. The circuit uses a single-ended
folded-cascode operational amplifier and two GM-C filters connected
in cascade. The circuit is realized in a 0.18 μm CMOS process and
offers differential to single-ended conversion. The novelty of the
scheme is the cascade of two GM-C filters to achieve a second-order
filter while minimizing power dissipation. The simulated filter cutoff
frequency is 1.14 kHz at common-mode voltage 1.65 V,
operating from a 3.3 V supply while dissipating 172μW of power.
The filter achieves an operating range of 1V for an output load of
1MOhm and 10pF.
Abstract: The 4G front-end transceiver needs a high
performance which can be obtained mainly with an optimal
architecture and a multi-band Local Oscillator. In this study, we
proposed and presented a new architecture of multi-band frequency
synthesizer based on an Inverse Sine Phase Detector Phase Locked
Loop (ISPD PLL) without any filters and any controlled gain block
and associated with adapted multi band LC tuned VCO using a
several numeric controlled capacitive branches but not binary
weighted. The proposed architecture, based on 0.35μm CMOS
process technology, supporting Multi-band GSM/DCS/DECT/
UMTS/WiMax application and gives a good performances: a phase
noise @1MHz -127dBc and a Factor Of Merit (FOM) @ 1MHz -
186dB and a wide band frequency range (from 0.83GHz to 3.5GHz),
that make the proposed architecture amenable for monolithic
integration and 4G multi-band application.
Abstract: In this report, an OTA which is used in fully
differential pipelined ADC was described. Using gain-boost
architecture with difference-ended amplifier, this OTA achieve
high-gain and high-speed. Besides, the CMFB circuit is also used, and
some methods are concerned to improve the performance. Then, by
optimization the layout design, OTA-s mismatch was reduced. This
design was using TSMC 0.18um CMOS process and simulation both
schematic and layout in Cadence. The result of the simulation shows
that the OTA has a gain up to 80dB,a unity gain bandwidth of about
1.437GHz for a 2pF load, a slew rate is about 428V/μs, a output swing
is 0.2V~1.35V, with the power supply of 1.8V, the power
consumption is 88mW. This amplifier was used in a 10bit 150MHz
pipelined ADC.
Abstract: We present a dual-band (Cellular & PCS) dual-path
zero-IF receiver for CDMA2000 diversity, monitoring and
simultaneous-GPS. The secondary path is a SAW-less diversity
CDMA receiver which can be also used for advanced features like
monitoring when supported with an additional external VCO. A GPS
receiver is integrated with its dedicated VCO allowing simultaneous
positioning during a cellular call. The circuit is implemented in a
0.25μm 40GHz-fT BiCMOS process and uses a HVQFN 56-pin
package. It consumes a maximum 300mW from a 2.8V supply in
dual-modes. The chip area is 12.8mm2.
Abstract: Displacement measurement was conducted on compact normal and shear specimens made of acrylic homogeneous material subjected to mixed-mode loading by digital image correlation. The intelligent hybrid method proposed by Nishioka et al. was applied to the stress-strain analysis near the crack tip. The accuracy of stress-intensity factor at the free surface was discussed from the viewpoint of both the experiment and 3-D finite element analysis. The surface images before and after deformation were taken by a CMOS camera, and we developed the system which enabled the real time stress analysis based on digital image correlation and inverse problem analysis. The great portion of processing time of this system was spent on displacement analysis. Then, we tried improvement in speed of this portion. In the case of cracked body, it is also possible to evaluate fracture mechanics parameters such as the J integral, the strain energy release rate, and the stress-intensity factor of mixed-mode. The 9-points elliptic paraboloid approximation could not analyze the displacement of submicron order with high accuracy. The analysis accuracy of displacement was improved considerably by introducing the Newton-Raphson method in consideration of deformation of a subset. The stress-intensity factor was evaluated with high accuracy of less than 1% of the error.
Abstract: A synchronous network-on-chip using wormhole packet switching
and supporting guaranteed-completion best-effort with low-priority (LP)
and high-priority (HP) wormhole packet delivery service is presented in
this paper. Both our proposed LP and HP message services deliver a good
quality of service in term of lossless packet completion and in-order message
data delivery. However, the LP message service does not guarantee minimal
completion bound. The HP packets will absolutely use 100% bandwidth of
their reserved links if the HP packets are injected from the source node with
maximum injection. Hence, the service are suitable for small size messages
(less than hundred bytes). Otherwise the other HP and LP messages, which
require also the links, will experience relatively high latency depending on the
size of the HP message. The LP packets are routed using a minimal adaptive
routing, while the HP packets are routed using a non-minimal adaptive routing
algorithm. Therefore, an additional 3-bit field, identifying the packet type,
is introduced in their packet headers to classify and to determine the type
of service committed to the packet. Our NoC prototypes have been also
synthesized using a 180-nm CMOS standard-cell technology to evaluate the
cost of implementing the combination of both services.
Abstract: This work aims to reduce the read power consumption
as well as to enhance the stability of the SRAM cell during the read
operation. A new 10-transisor cell is proposed with a new read
scheme to minimize the power consumption within the memory core.
It has separate read and write ports, thus cell read stability is
significantly improved. A 16Kb SRAM macro operating at 1V
supply voltage is demonstrated in 65 nm CMOS process. Its read
power consumption is reduced to 24% of the conventional design.
The new cell also has lower leakage current due to its special bit-line
pre-charge scheme. As a result, it is suitable for low-power mobile
applications where power supply is restricted by the battery.
Abstract: A high precision temperature insensitive current and voltage reference generator is presented. It is specifically developed for temperature compensated oscillator. The circuit, designed using MXIC 0.5um CMOS technology, has an operating voltage that ranges from 2.6V to 5V and generates a voltage of 1.21V and a current of 6.38 ӴA. It exhibits a variation of ±0.3nA for the current reference and a stable output for voltage reference as the temperature is varied from 0°C to 70°C. The power supply rejection ratio obtained without any filtering capacitor at 100Hz and 10MHz is -30dB and -12dB respectively.
Abstract: In this paper a novel high output impedance, low input impedance, wide bandwidth, very simple current mirror with input and output voltage requirements less than that of a simple current mirror is presented. These features are achieved with very simple structure avoiding extra large node impedances to ensure high bandwidth operation. The circuit's principle of operation is discussed and compared to simple and low voltage cascode (LVC) current mirrors. Such outstanding features of this current mirror as high output impedance ~384K, low input impedance~6.4, wide bandwidth~178MHz, low input voltage ~ 362mV, low output voltage ~ 38mV and low current transfer error ~4% (all at 50μA) makes it an outstanding choice for high performance applications. Simulation results in BSIM 0.35μm CMOS technology with HSPICE are given in comparison with simple, and LVC current mirrors to verify and validate the performance of the proposed current mirror.
Abstract: Structural representation and technology mapping of
a Boolean function is an important problem in the design of nonregenerative
digital logic circuits (also called combinational logic
circuits). Library aware function manipulation offers a solution to
this problem. Compact multi-level representation of binary networks,
based on simple circuit structures, such as AND-Inverter Graphs
(AIG) [1] [5], NAND Graphs, OR-Inverter Graphs (OIG), AND-OR
Graphs (AOG), AND-OR-Inverter Graphs (AOIG), AND-XORInverter
Graphs, Reduced Boolean Circuits [8] does exist in
literature. In this work, we discuss a novel and efficient graph
realization for combinational logic circuits, represented using a
NAND-NOR-Inverter Graph (NNIG), which is composed of only
two-input NAND (NAND2), NOR (NOR2) and inverter (INV) cells.
The networks are constructed on the basis of irredundant disjunctive
and conjunctive normal forms, after factoring, comprising terms with
minimum support. Construction of a NNIG for a non-regenerative
function in normal form would be straightforward, whereas for the
complementary phase, it would be developed by considering a virtual
instance of the function. However, the choice of best NNIG for a
given function would be based upon literal count, cell count and
DAG node count of the implementation at the technology
independent stage. In case of a tie, the final decision would be made
after extracting the physical design parameters.
We have considered AIG representation for reduced disjunctive
normal form and the best of OIG/AOG/AOIG for the minimized
conjunctive normal forms. This is necessitated due to the nature of
certain functions, such as Achilles- heel functions. NNIGs are found
to exhibit 3.97% lesser node count compared to AIGs and
OIG/AOG/AOIGs; consume 23.74% and 10.79% lesser library cells
than AIGs and OIG/AOG/AOIGs for the various samples considered.
We compare the power efficiency and delay improvement achieved
by optimal NNIGs over minimal AIGs and OIG/AOG/AOIGs for
various case studies. In comparison with functionally equivalent,
irredundant and compact AIGs, NNIGs report mean savings in power
and delay of 43.71% and 25.85% respectively, after technology
mapping with a 0.35 micron TSMC CMOS process. For a
comparison with OIG/AOG/AOIGs, NNIGs demonstrate average
savings in power and delay by 47.51% and 24.83%. With respect to
device count needed for implementation with static CMOS logic
style, NNIGs utilize 37.85% and 33.95% lesser transistors than their
AIG and OIG/AOG/AOIG counterparts.
Abstract: As embedded and portable systems were emerged power consumption of circuits had been major challenge. On the other hand latency as determines frequency of circuits is also vital task. Therefore, trade off between both of them will be desirable. Modulo 2n+1 adders are important part of the residue number system (RNS) based arithmetic units with the interesting moduli set (2n-1,2n, 2n+1). In this manuscript we have introduced novel binary representation to the design of modulo 2n+1 adder. VLSI realization of proposed architecture under 180 nm full static CMOS technology reveals its superiority in terms of area, power consumption and power-delay product (PDP) against several peer existing structures.
Abstract: This paper presents two prototypes of low power low voltage current mode 9 bit pipelined a/d converters. The first and the second converters are configured of 1.5 bit and 2.5 bit stages, respectively. The a/d converter structures are composed of current mode building blocks and final comparator block which converts the analog current signal into digital voltage signal. All building blocks have been designed in CMOS AMS 0.35μm technology, then simulated to verify proposed concept. The performances of both converters are compared to performances of known current mode and voltage mode switched capacitance converter structures. Low power consumption and small chip area are advantages of the proposed converters.
Abstract: A precision CMOS chopping amplifier is adopted in this work to improve a CMOS temperature sensor high sensitive enough for intracranial temperature monitoring. An amplified temperature sensitivity of 18.8 ± 3*0.2 mV/oC is attained over the temperature range from 20 oC to 80 oC from a given 10 samples of the same wafer. The analog frontend design outputs the temperature dependent and the temperature independent signals which can be directly interfaced to a 10 bit ADC to accomplish an accurate temperature instrumentation system.
Abstract: A digital system is proposed for low power 100-
channel neural recording system in this paper, which consists of 100
amplifiers, 100 analog-to-digital converters (ADC), digital controller
and baseband, transceiver for data link and RF command link. The
proposed system is designed in a 0.18 μm CMOS process and 65 nm
CMOS process.
Abstract: This paper presents a low-voltage low-power differential linear transconductor with near rail-to-rail input swing. Based on the current-mirror OTA topology, the proposed transconductor combines the Flipped Voltage Follower (FVF) technique to linearize the transconductor behavior that leads to class- AB linear operation and the virtual transistor technique to lower the effective threshold voltages of the transistors which offers an advantage in terms of low supply requirement. Design of the OTA has been discussed. It operates at supply voltages of about ±0.8V. Simulation results for 0.18μm TSMC CMOS technology show a good input range of 1Vpp with a high DC gain of 81.53dB and a total harmonic distortion of -40dB at 1MHz for an input of 1Vpp. The main aim of this paper is to present and compare new OTA design with high transconductance, which has a potential to be used in low voltage applications.
Abstract: This paper describes a 2.4 GHz passive switch mixer
and a 5/2.5 GHz voltage-controlled negative Gm oscillator (VCO)
with an inversion-mode MOS varactor. Both circuits are implemented
using a 1P8M 0.13 μm process. The switch mixer has an input
referred 1 dB compression point of -3.89 dBm and a conversion
gain of -0.96 dB when the local oscillator power is +2.5 dBm.
The VCO consumes only 1.75 mW, while drawing 1.45 mA from a
1.2 V supply voltage. In order to reduce the passives size, the VCO
natural oscillation frequency is 5 GHz. A clocked CMOS divideby-
two circuit is used for frequency division and quadrature phase
generation. The VCO has a -109 dBc/Hz phase noise at 1 MHz
frequency offset and a 2.35-2.5 GHz tuning range (after the frequency
division), thus complying with ZigBee requirements.
Abstract: An on chip low drop out voltage regulator that
employs elegant compensation scheme is presented in this paper. The
novelty in this design is that the device parasitic capacitances are
exploited for compensation at different loads. The proposed LDO is
designed to provide a constant voltage of 1.2V and is implemented in
UMC 180 nano meter CMOS technology. The voltage regulator
presented improves stability even at lighter loads and enhances line
and load regulation.
Abstract: Reversible logic is becoming more and more prominent
as the technology sets higher demands on heat, power, scaling
and stability. Reversible gates are able at any time to "undo" the
current step or function. Multiple-valued logic has the advantage of
transporting and evaluating higher bits each clock cycle than binary.
Moreover, we demonstrate in this paper, combining these disciplines
we can construct powerful multiple-valued reversible logic structures.
In this paper a reversible block implemented by pseudo floatinggate
can perform AD-function and a DA-function as its reverse
application.
Abstract: In this paper we present an energy efficient match-line
(ML) sensing scheme for high-speed ternary content-addressable
memory (TCAM). The proposed scheme isolates the sensing unit of
the sense amplifier from the large and variable ML capacitance. It
employs feedback in the sense amplifier to successfully detect a
match while keeping the ML voltage swing low. This reduced voltage
swing results in large energy saving. Simulation performed using
130nm 1.2V CMOS logic shows at least 30% total energy saving in
our scheme compared to popular current race (CR) scheme for
similar search speed. In terms of speed, dynamic energy, peak power
consumption and transistor count our scheme also shows better
performance than mismatch-dependant (MD) power allocation
technique which also employs feedback in the sense amplifier.
Additionally, the implementation of our scheme is simpler than CR
or MD scheme because of absence of analog control voltage and
programmable delay circuit as have been used in those schemes.
Abstract: Full adders are important components in applications
such as digital signal processors (DSP) architectures and
microprocessors. In addition to its main task, which is adding two
numbers, it participates in many other useful operations such as
subtraction, multiplication, division,, address calculation,..etc. In
most of these systems the adder lies in the critical path that
determines the overall speed of the system. So enhancing the
performance of the 1-bit full adder cell (the building block of the
adder) is a significant goal.Demands for the low power VLSI have
been pushing the development of aggressive design methodologies to
reduce the power consumption drastically. To meet the growing
demand, we propose a new low power adder cell by sacrificing the
MOS Transistor count that reduces the serious threshold loss
problem, considerably increases the speed and decreases the power
when compared to the static energy recovery full (SERF) adder. So a
new improved 14T CMOS l-bit full adder cell is presented in this
paper. Results show 50% improvement in threshold loss problem,
45% improvement in speed and considerable power consumption
over the SERF adder and other different types of adders with
comparable performance.