A Reversible CMOS AD / DA Converter Implemented with Pseudo Floating-Gate

Reversible logic is becoming more and more prominent as the technology sets higher demands on heat, power, scaling and stability. Reversible gates are able at any time to "undo" the current step or function. Multiple-valued logic has the advantage of transporting and evaluating higher bits each clock cycle than binary. Moreover, we demonstrate in this paper, combining these disciplines we can construct powerful multiple-valued reversible logic structures. In this paper a reversible block implemented by pseudo floatinggate can perform AD-function and a DA-function as its reverse application.

Automation of Packing Cell in Fresh Fish Facilities

The problem discussed in this paper involves packing fresh fish fileet of the northern Cod into a standard square container. The fish is first cleaned and split and then collected on a belt ready to be stacked in a container. The aim of our work is to pack the fish into the container with constraints on the amount of overlap allowed for the fileets. The current focus is to design a packing cell that can be real-time and of practical use, while finding the optimal solution to the degree of overlap and minimise the unused space of the container.

Novel Mobile Climbing Robot Agent for Offshore Platforms

To improve HSE standards, oil and gas industries are interested in using remotely controlled and autonomous robots instead of human workers on offshore platforms. In addition to earlier reason this strategy would increase potential revenue, efficient usage of work experts and even would allow operations in more remote areas. This article is the presentation of a custom climbing robot, called Walloid, designed for offshore platform topside automation. This 4 arms climbing robot with grippers is an ongoing project at University of Oslo.

High Speed and Ultra Low-voltage CMOS NAND and NOR Domino Gates

In this paper we ultra low-voltage and high speed CMOS domino logic. For supply voltages below 500mV the delay for a ultra low-voltage NAND2 gate is aproximately 10% of a complementary CMOS inverter. Furthermore, the delay variations due to mismatch is much less than for conventional CMOS. Differential domino gates for AND/NAND and OR/NOR operation are presented.