Abstract: This work presents a fully differential CMOS amplifier consisting of two self-biased gain boosted inverter stages, that provides an alternative to the power hungry operational amplifier. The self-biasing avoids the use of external biasing circuitry, thus reduces the die area, design efforts, and power consumption. In the present work, regulated cascode technique has been employed for gain boosting. The Miller compensation is also applied to enhance the phase margin. The circuit has been designed and simulated in 1.8 V 0.18 µm CMOS technology. The simulation results show a high DC gain of 100.7 dB, Unity-Gain Bandwidth of 107.8 MHz, and Phase Margin of 66.7o with a power dissipation of 286 μW and makes it suitable candidate for the high resolution pipelined ADCs.
Abstract: This paper presents a 14-bit cyclic-pipelined Analog to digital converter (ADC) running at 1 MS/s. The architecture is based on a 1.5-bit per stage structure utilizing digital correction for each stage. The ADC consists of two 1.5-bit stages, one shift register delay line, and digital error correction logic. Inside each 1.5-bit stage, there is one gain-boosting op-amp and two comparators. The ADC was implemented in 0.18µm CMOS process and the design has an area of approximately 0.2 mm2. The ADC has a differential input range of 1.2 Vpp. The circuit has an average power consumption of 3.5mA with 10MHz sampling clocks. The post-layout simulations of the design satisfy 12-bit SNDR with a full-scale sinusoid input.
Abstract: In this report, an OTA which is used in fully
differential pipelined ADC was described. Using gain-boost
architecture with difference-ended amplifier, this OTA achieve
high-gain and high-speed. Besides, the CMFB circuit is also used, and
some methods are concerned to improve the performance. Then, by
optimization the layout design, OTA-s mismatch was reduced. This
design was using TSMC 0.18um CMOS process and simulation both
schematic and layout in Cadence. The result of the simulation shows
that the OTA has a gain up to 80dB,a unity gain bandwidth of about
1.437GHz for a 2pF load, a slew rate is about 428V/μs, a output swing
is 0.2V~1.35V, with the power supply of 1.8V, the power
consumption is 88mW. This amplifier was used in a 10bit 150MHz
pipelined ADC.
Abstract: A 3.5-bit stage of the CMOS pipelined ADC is proposed. In this report, the main part of 3.5-bit stage ADC is introduced. How the MDAC, comparator and encoder worked and designed are shown in details. Besides, an OTA which is used in fully differential pipelined ADC was described. Using gain-boost architecture with differential amplifier, this OTA achieve high-gain and high-speed. This design was using CMOS 0.18um process and simulation in Cadence. The result of the simulation shows that the OTA has a gain up to 80dB, the unity gain bandwidth of about 1.138GHz with 2pF load.
Abstract: Pipeline ADCs are becoming popular at high speeds
and with high resolution. This paper discusses the options of number
of bits/stage conversion techniques in pipelined ADCs and their
effect on Area, Speed, Power Dissipation and Linearity. The basic
building blocks like op-amp, Sample and Hold Circuit, sub converter,
DAC, Residue Amplifier used in every stage is assumed to be
identical. The sub converters use flash architectures. The design is
implemented using 0.18