Card image

Scholarly

Volume:7, Issue: 9, 2013 Page No: 1193 - 1196

International Journal of Electrical, Electronic and Communication Sciences

ISSN: 2517-9438

2629 Downloads
Abstract Full Text Download References Share Add to Favorites
DOI:10.5281/zenodo.1335642 BibTeX JSON

14-Bit 1MS/s Cyclic-Pipelined ADC

This paper presents a 14-bit cyclic-pipelined Analog to digital converter (ADC) running at 1 MS/s. The architecture is based on a 1.5-bit per stage structure utilizing digital correction for each stage. The ADC consists of two 1.5-bit stages, one shift register delay line, and digital error correction logic. Inside each 1.5-bit stage, there is one gain-boosting op-amp and two comparators. The ADC was implemented in 0.18µm CMOS process and the design has an area of approximately 0.2 mm2. The ADC has a differential input range of 1.2 Vpp. The circuit has an average power consumption of 3.5mA with 10MHz sampling clocks. The post-layout simulations of the design satisfy 12-bit SNDR with a full-scale sinusoid input.


Authors:
Keywords:
References:
[1] S. M. Chen and R. W. Brodersen, “A 6-bit 600-MS/s 5.3-mW
asynchronous ADC in 0.13-um CMOS,” in IEEE J. Solid-State Circuits,
vol.41, no. 12, pp. 2669–2680, Dec. 2006.
[2] J. Craninckx and G. Van der Plas, “A 65 fJ/conv.-step 0-to-50 Ms/s 0-to-
0.7 mW 9b charge-sharing SAR ADC in 90 nm digital CMOS,”in IEEE
ISSCC Dig. Tech. Papers, 2007, pp. 246–247
[3] Chun C. Lee and Michael P. Flynn, “A SAR-Assisted Two-Stage
Pipeline ADC” in IEEE J. Solid-State Circuits, vol.46, no. 4,pp. 859-
869, Apr. 2011
[4] Shan Jiang, Manh Anh Do, Kiat Seng Yeo and Wei Meng Lim, “An 8-
bit 200-MSample/s Pipelined ADC With Mixed-Mode Front-End S/H
Circuit” in IEEE Transaction on Circuits and systems I, vol.55, no. 6,
pp. 1430-1440, Jul. 2008.
[5] V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. Van der Plas, and
J. Craninckx, “An 820uW 9b 40 MS/s noise-tolerant dynamic-SAR
ADC in a 90 nm digital CMOS process,” in IEEE ISSCC Dig.
Tech.Papers, 2008, pp. 238–239.