Optimizing the Number of Bits/Stage in 10-Bit, 50Ms/Sec Pipelined A/D Converter Considering Area, Speed, Power and Linearity
Pipeline ADCs are becoming popular at high speeds
and with high resolution. This paper discusses the options of number
of bits/stage conversion techniques in pipelined ADCs and their
effect on Area, Speed, Power Dissipation and Linearity. The basic
building blocks like op-amp, Sample and Hold Circuit, sub converter,
DAC, Residue Amplifier used in every stage is assumed to be
identical. The sub converters use flash architectures. The design is
implemented using 0.18
[1] R. Jacob Baker, CMOS mixed signal circuit design, 2nd ed., IEEE press,
2003.
[2] Rudy van de Plassey., CMOS Analog-to- Digital and Digital-to-analog
Converters, : Springer, 2005.
[3] David A Johns and Ken Martin, Analog integrated circuit design. 2005.
[4] Behzad Razavi, Design of Analog CMOS Integrated circuits,TMH 2002.
[5] Jipeng Li and Un-Ku Moon, "A 1.8V 67mW 10bit 100 M/S Pipelined
ADC using time shifted CDS technique," IEEE J solid state circuits,vol
39 pp. 1468-1476, September 2004.
[6] Thomas Byunghak Cho, Paul R.Gray, "A10b, 20 Msample/s, 35 mW
Pipeline A/D Converter", IEEE Journal of Solid State Circuits, Vol. 30,
No.3, March 1995.
[7] J. K. Fiorenza, T. Sepke, P. Holloway, C.G. Sodini and H.S. Lee,
"Comparator based switched capacitor circuits for scaled CMOS
technologies", IEEE Solid State Circuits, Vol. 41, no. 12, pp. 2658-
2668, Dec. 2006.
[8] L. Brooks and H. S. Lee, "A Zero crossing based 8b, 200 MS/s pipelined
ADC", in IEEE ISSCC Dig. Tech Papers, pp. 460-461.
[9] J. G. Peterson, "A Monolithic Video A/D Converter," IEEE J. Solidstate
Circuits, vol. SC-14, pp. 932-937, Dec. 1979.
[10] S. H. Lewis et al., "A pipelined 9-stage video-rate analog-to-digital
converter," IEEE J . Solid-state Circuits, vol. 27, pp. 351-358, Mar.1992
[11] K. Hadidi, G. C. Temes, and K. W. Martin, "Error analysis and digital
correction algorithms for pipelined A/D converters," Dig.Tech. Papers,
1990 IEEE Int. Symp. Circuits and Systems, pp.1709-1712, May 1990.
[12] T. Matsuura et al., "An 8b 20MHz CMOS half-flash A/D converter,"
Dig. Tech. Papers, IEEE Int. Solid-state Circuits Conf., pp. 220-221,
Feb. 1988.
[1] R. Jacob Baker, CMOS mixed signal circuit design, 2nd ed., IEEE press,
2003.
[2] Rudy van de Plassey., CMOS Analog-to- Digital and Digital-to-analog
Converters, : Springer, 2005.
[3] David A Johns and Ken Martin, Analog integrated circuit design. 2005.
[4] Behzad Razavi, Design of Analog CMOS Integrated circuits,TMH 2002.
[5] Jipeng Li and Un-Ku Moon, "A 1.8V 67mW 10bit 100 M/S Pipelined
ADC using time shifted CDS technique," IEEE J solid state circuits,vol
39 pp. 1468-1476, September 2004.
[6] Thomas Byunghak Cho, Paul R.Gray, "A10b, 20 Msample/s, 35 mW
Pipeline A/D Converter", IEEE Journal of Solid State Circuits, Vol. 30,
No.3, March 1995.
[7] J. K. Fiorenza, T. Sepke, P. Holloway, C.G. Sodini and H.S. Lee,
"Comparator based switched capacitor circuits for scaled CMOS
technologies", IEEE Solid State Circuits, Vol. 41, no. 12, pp. 2658-
2668, Dec. 2006.
[8] L. Brooks and H. S. Lee, "A Zero crossing based 8b, 200 MS/s pipelined
ADC", in IEEE ISSCC Dig. Tech Papers, pp. 460-461.
[9] J. G. Peterson, "A Monolithic Video A/D Converter," IEEE J. Solidstate
Circuits, vol. SC-14, pp. 932-937, Dec. 1979.
[10] S. H. Lewis et al., "A pipelined 9-stage video-rate analog-to-digital
converter," IEEE J . Solid-state Circuits, vol. 27, pp. 351-358, Mar.1992
[11] K. Hadidi, G. C. Temes, and K. W. Martin, "Error analysis and digital
correction algorithms for pipelined A/D converters," Dig.Tech. Papers,
1990 IEEE Int. Symp. Circuits and Systems, pp.1709-1712, May 1990.
[12] T. Matsuura et al., "An 8b 20MHz CMOS half-flash A/D converter,"
Dig. Tech. Papers, IEEE Int. Solid-state Circuits Conf., pp. 220-221,
Feb. 1988.
@article{"International Journal of Electrical, Electronic and Communication Sciences:58357", author = "P. Prasad Rao and K. Lal Kishore", title = "Optimizing the Number of Bits/Stage in 10-Bit, 50Ms/Sec Pipelined A/D Converter Considering Area, Speed, Power and Linearity", abstract = "Pipeline ADCs are becoming popular at high speeds
and with high resolution. This paper discusses the options of number
of bits/stage conversion techniques in pipelined ADCs and their
effect on Area, Speed, Power Dissipation and Linearity. The basic
building blocks like op-amp, Sample and Hold Circuit, sub converter,
DAC, Residue Amplifier used in every stage is assumed to be
identical. The sub converters use flash architectures. The design is
implemented using 0.18", keywords = "1.5 bits/stage, Conversion Frequency, Redundancy
Switched Capacitor Sample and Hold Circuit", volume = "6", number = "2", pages = "209-7", }