Abstract: The most important mathematical operation for any computing system is addition. An efficient adder can be of greater assistance in designing of any arithmetic circuits. Quantum-dot Cellular Automata (QCA) is a promising nanotechnology to create electronic circuits for computing devices and suitable candidate for next generation of computing systems. The article presents a modest approach to implement a novel XOR gate. The gate is simple in structure and powerful in terms of implementing digital circuits. By applying the XOR gate, the hardware requirement for a QCA circuit can be decrease and circuits can be simpler in level, clock phase and cell count. In order to verify the functionality of the proposed device some implementation of Half Adder (HA) and Full Adder (FA) is checked by means of computer simulations using QCA-Designer tool. Simulation results and physical relations confirm its usefulness in implementing every digital circuit.
Abstract: This paper describes about dynamic reconfiguration to
miniaturize arithmetic circuits in general-purpose processor. Dynamic
reconfiguration is a technique to realize required functions by
changing hardware construction during operation. The proposed
arithmetic circuit performs floating-point arithmetic which is
frequently used in science and technology. The data format is
floating-point based on IEEE754. The proposed circuit is designed
using VHDL, and verified the correct operation by simulations and
experiments.
Abstract: Full adders are important components in applications
such as digital signal processors (DSP) architectures and
microprocessors. In addition to its main task, which is adding two
numbers, it participates in many other useful operations such as
subtraction, multiplication, division,, address calculation,..etc. In
most of these systems the adder lies in the critical path that
determines the overall speed of the system. So enhancing the
performance of the 1-bit full adder cell (the building block of the
adder) is a significant goal.Demands for the low power VLSI have
been pushing the development of aggressive design methodologies to
reduce the power consumption drastically. To meet the growing
demand, we propose a new low power adder cell by sacrificing the
MOS Transistor count that reduces the serious threshold loss
problem, considerably increases the speed and decreases the power
when compared to the static energy recovery full (SERF) adder. So a
new improved 14T CMOS l-bit full adder cell is presented in this
paper. Results show 50% improvement in threshold loss problem,
45% improvement in speed and considerable power consumption
over the SERF adder and other different types of adders with
comparable performance.
Abstract: New methodologies for XOR-XNOR circuits are
proposed to improve the speed and power as these circuits are basic
building blocks of many arithmetic circuits. This paper evaluates and
compares the performance of various XOR-XNOR circuits. The
performance of the XOR-XNOR circuits based on TSMC 0.18μm
process models at all range of the supply voltage starting from 0.6V
to 3.3V is evaluated by the comparison of the simulation results
obtained from HSPICE. Simulation results reveal that the proposed
circuit exhibit lower PDP and EDP, more power efficient and faster
when compared with best available XOR-XNOR circuits in the
literature.
Abstract: This paper proposes an architecture of dynamically
reconfigurable arithmetic circuit. Dynamic reconfiguration is a
technique to realize required functions by changing hardware
construction during operations. The proposed circuit is based on a
complex number multiply-accumulation circuit which is used
frequently in the field of digital signal processing. In addition, the
proposed circuit performs real number double precision arithmetic
operations. The data formats are single and double precision floating
point number based on IEEE754. The proposed circuit is designed
using VHDL, and verified the correct operation by simulations and
experiments.