Abstract: Paper presents a low power, high speed, sense-amplifier based flip-flop (SAFF). The flip-flop’s power con-sumption and delay are greatly reduced by employing a new conditionally precharge sense-amplifier stage and a single-ended latch stage. Glitch-free and contention-free latch operation is achieved by using a conditional cut-off strategy. The design uses fewer transistors, has a lower clock load, and has a simple structure, all of which contribute to a near-zero setup time. When compared to previous flip-flop structures proposed for similar input/output conditions, this design’s performance and overall PDP have improved. The post layout simulation of the circuit uses 2.91µW of power and has a delay of 65.82 ps. Overall, the power-delay product has seen some enhancements. Cadence Virtuoso Designing tool with CMOS 90nm technology are used for all designs.
Abstract: This paper discusses the undesirable charge transfer
through the parasitic capacitances of the input transistors in a
multi-inputs voltage sense amplifier. Its intrinsic rail-to-rail voltage
transitions at the output nodes inevitably disturb the input sides
through the capacitive coupling between the outputs and inputs. Then,
it can possible degrade the stabilities of the reference voltage levels.
Moreover, it becomes more serious in multi-channel systems by
altering them for other channels, and so degrades the linearity of the
overall systems. In order to alleviate the internal node voltage
transition, the internal node stabilization techniques are proposed. It
achieves 45% and 40% improvements for node stabilization and input
referred disturbance, respectively.
Abstract: This paper discusses the undesirable charge transfer by the parasitic capacitances of the input transistors in a voltage sense amplifier. Due to its intrinsic rail-to-rail voltage transition, the input sides are inevitably disturbed. It can possible disturb the stabilities of the reference voltage levels. Moreover, it becomes serious in multi-channel systems by altering them for other channels, and so degrades the linearity of the systems. In order to alleviate the internal node voltage transition, the internal node stabilization technique is proposed by utilizing an additional biasing circuit. It achieves 47% and 43% improvements for node stabilization and input referred disturbance, respectively.
Abstract: In this paper we present an energy efficient match-line
(ML) sensing scheme for high-speed ternary content-addressable
memory (TCAM). The proposed scheme isolates the sensing unit of
the sense amplifier from the large and variable ML capacitance. It
employs feedback in the sense amplifier to successfully detect a
match while keeping the ML voltage swing low. This reduced voltage
swing results in large energy saving. Simulation performed using
130nm 1.2V CMOS logic shows at least 30% total energy saving in
our scheme compared to popular current race (CR) scheme for
similar search speed. In terms of speed, dynamic energy, peak power
consumption and transistor count our scheme also shows better
performance than mismatch-dependant (MD) power allocation
technique which also employs feedback in the sense amplifier.
Additionally, the implementation of our scheme is simpler than CR
or MD scheme because of absence of analog control voltage and
programmable delay circuit as have been used in those schemes.