A Novel Nano-Scaled SRAM Cell

To help overcome limits to the density of conventional SRAMs and leakage current of SRAM cell in nanoscaled CMOS technology, we have developed a four-transistor SRAM cell. The newly developed CMOS four-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 19% smaller than a conventional six-transistor cell using same design rules. Also the leakage current of new cell is 60% smaller than a conventional sixtransistor SRAM cell. Simulation result in 65nm CMOS technology shows new cell has correct operation during read/write operation and idle mode.

• Arash Azizi Mazreah
• Mohammad Reza Sahebi
• Mohammad T. Manzuri Shalmani

• SRAM Cell
• leakage current
• cell area.

[1] Y. J. Chang, F. Lai, and Ch. L. Yang, "Zero-Aware Asymmetric SRAM
Cell for Reducing Cache Power in Writing Zero", IEEE Trans. On VLSI
system, vol. 12, no. 8, pp. 827-836, August 2004.
[2] A. Kotabe et al., "A Low-Power Four-Transistor SRAM Cell With a
Stacked Vertical Poly-Silicon PMOS and a Dual-Word-Voltage
Scheme," IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 870-876, April
2005.
[3] B. Amelifard, F. Fallah, M. Pedram, "Low-leakage SRAM design with
dual Vt transistors," 7th Int'l Symp. on Quality of Electronic Designs,
2006.
[4] A. Azizi Mazreah, M. T. Manzuri Shalmani, et al., "A novel zero-aware
read-static-noise-margin-free SRAM cell for high density and high speed
cache application," in Proc. 9th International Conference on Solid-State
and Integrated-Circuit Technology (ICSICT-08), October 2008, pp. 876-
879.
[5] A. Azizi Mazreah, M. T. Manzuri et al., "A High Density and Low
Power Cache Based on Novel SRAM Cell," Journal of Computers, vol.
4, no. 7, pp. 567-575, 2009.
[6] http://www.eas.asu.edu/~ptm & W. Zhao and Y. Cao, "New generation
of predictive technology model for sub- 45nm design exploration," IEEE
Trans. on Electron Devices, vol. 53, no. 11, pp. 2816-2823, November
2006.
[7] N. Azizi, F. Najm, and A. Moshovos, "Low-leakage asymmetric-cell
SRAM," IEEE Trans. on Very Large Scale Integration Systems, vol. 11,
no. 4, pp. 701-715, August 2003.