Abstract: In this paper, a two-stage op-amp design is considered using both Miller and negative Miller compensation techniques. The first op-amp design uses Miller compensation around the second amplification stage, whilst the second op-amp design uses negative Miller compensation around the first stage and Miller compensation around the second amplification stage. The aims of this work were to compare the gain and phase margins obtained using the different compensation techniques and identify the ability to choose either compensation technique based on a particular set of design requirements. The two op-amp designs created are based on the same two-stage rail-to-rail output CMOS op-amp architecture where the first stage of the op-amp consists of differential input and cascode circuits, and the second stage is a class AB amplifier. The op-amps have been designed using a 0.35mm CMOS fabrication process.
Abstract: This work presents a fully differential CMOS amplifier consisting of two self-biased gain boosted inverter stages, that provides an alternative to the power hungry operational amplifier. The self-biasing avoids the use of external biasing circuitry, thus reduces the die area, design efforts, and power consumption. In the present work, regulated cascode technique has been employed for gain boosting. The Miller compensation is also applied to enhance the phase margin. The circuit has been designed and simulated in 1.8 V 0.18 µm CMOS technology. The simulation results show a high DC gain of 100.7 dB, Unity-Gain Bandwidth of 107.8 MHz, and Phase Margin of 66.7o with a power dissipation of 286 μW and makes it suitable candidate for the high resolution pipelined ADCs.
Abstract: This paper presents comparison among methods of
determination of the characteristic polynomial coefficients. First, the
resultant systems from the methods are compared based on frequency
criteria such as the closed loop bandwidth, gain and phase margins.
Then the step responses of the resultant systems are compared on the
basis of the transient behavior criteria including overshoot, rise time,
settling time and error (via IAE, ITAE, ISE and ITSE integral
indices). Also relative stability of the systems is compared together.
Finally the best choices in regards to the above diverse criteria are
presented.
Abstract: This paper presents the design and layout of a two stage, high speed operational amplifiers using standard 0.35um CMOS technology. The design procedure involves designing the bias circuit, the differential input pair, and the gain stage using CAD tools. Both schematic and layout of the operational amplifier along with the comparison in the results of the two has been presented. The operational amplifier designed, has a gain of 93.51db at low frequencies. It has a gain bandwidth product of 55.07MHz, phase margin of 51.9º and a slew rate of 22v/us for a load of capacitor of 10pF.
Abstract: To achieve the desired specifications of gain and
phase margins for plants with time-delay that stabilized with FO-PID
controller a lead compensator is designed. At first the range of
controlled system stability based on stability boundary criteria is
determined. Using stability boundary locus method in frequency
domain the fractional order controller parameters are tuned and then
with drawing bode diagram in frequency domain accessing to desired
gain and phase margin are shown. Numerical examples are given to
illustrate the shapes of the stabilizing region and to show the design
procedure.
Abstract: This paper proposes the analysis and design of robust
fuzzy control to Stochastic Parametrics Uncertaint Linear systems.
This system type to be controlled is partitioned into several linear
sub-models, in terms of transfer function, forming a convex polytope,
similar to LPV (Linear Parameters Varying) system. Once defined the
linear sub-models of the plant, these are organized into fuzzy Takagi-
Sugeno (TS) structure. From the Parallel Distributed Compensation
(PDC) strategy, a mathematical formulation is defined in the frequency
domain, based on the gain and phase margins specifications,
to obtain robust PI sub-controllers in accordance to the Takagi-
Sugeno fuzzy model of the plant. The main results of the paper are
based on the robust stability conditions with the proposal of one
Axiom and two Theorems.
Abstract: Fractional-order controller was proven to perform better than the integer-order controller. However, the absence of a pole at origin produced marginal error in fractional-order control system. This study demonstrated the enhancement of the fractionalorder PI over the integer-order PI in a steam temperature control. The fractional-order controller was cascaded with an error compensator comprised of a very small zero and a pole at origin to produce a zero steady-state error for the closed-loop system. Some modification on the error compensator was suggested for different order fractional integrator that can improve the overall phase margin.
Abstract: A 10bit, 40 MSps, sample and hold, implemented in 0.18-μm CMOS technology with 3.3V supply, is presented for application in the front-end stage of an analog-to-digital converter. Topology selection, biasing, compensation and common mode feedback are discussed. Cascode technique has been used to increase the dc gain. The proposed opamp provides 149MHz unity-gain bandwidth (wu), 80 degree phase margin and a differential peak to peak output swing more than 2.5v. The circuit has 55db Total Harmonic Distortion (THD), using the improved fully differential two stage operational amplifier of 91.7dB gain. The power dissipation of the designed sample and hold is 4.7mw. The designed system demonstrates relatively suitable response in different process, temperature and supply corners (PVT corners).
Abstract: A fully on-chip low drop-out (LDO) voltage regulator with 100pF output load capacitor is presented. A novel frequency compensation scheme using current buffer is adopted to realize single dominant pole within the unit gain frequency of the regulation loop, the phase margin (PM) is at least 50 degree under the full range of the load current, and the power supply rejection (PSR) character is improved compared with conventional Miller compensation. Besides, the differentiator provides a high speed path during the load current transient. Implemented in 0.18μm CMOS technology, the LDO voltage regulator provides 100mA load current with a stable 1.8V output voltage consuming 80μA quiescent current.