Abstract: In this study, Li4SiO4 powder was successfully
synthesized via sol gel method followed by drying at 150oC. Lithium
oxide, Li2O and silicon oxide, SiO2 were used as the starting
materials with citric acid as the chelating agent. The obtained powder
was then sintered at various temperatures. Crystallographic phase
analysis, morphology and ionic conductivity were investigated
systematically employing X-ray diffraction, Fourier Transform
Infrared, Scanning Electron Microscopy and AC impedance
spectroscopy. XRD result showed the formation of pure monoclinic
Li4SiO4 crystal structure with lattice parameters a = 5.140 Å, b =
6.094 Å, c = 5.293 Å, β = 90o in the sample sintered at 750oC. This
observation was confirmed by FTIR analysis. The bulk conductivity
of this sample at room temperature was 3.35 × 10-6 S cm-1 and the
highest bulk conductivity of 1.16 × 10-4 S cm-1 was obtained at
100°C. The results indicated that, the Li4SiO4 compound has
potential to be used as host for LISICON structured solid electrolyte
for low temperature application.
Abstract: As in today's semiconductor industries test costs can make up to 50 percent of the total production costs, an efficient test error detection becomes more and more important. In this paper, we present a new machine learning approach to test error detection that should provide a faster recognition of test system faults as well as an improved test error recall. The key idea is to learn a classifier ensemble, detecting typical test error patterns in wafer test results immediately after finishing these tests. Since test error detection has not yet been discussed in the machine learning community, we define central problem-relevant terms and provide an analysis of important domain properties. Finally, we present comparative studies reflecting the failure detection performance of three individual classifiers and three ensemble methods based upon them. As base classifiers we chose a decision tree learner, a support vector machine and a Bayesian network, while the compared ensemble methods were simple and weighted majority vote as well as stacking. For the evaluation, we used cross validation and a specially designed practical simulation. By implementing our approach in a semiconductor test department for the observation of two products, we proofed its practical applicability.
Abstract: This paper presents the experimental results of salt fog ageing test of silicone rubber housing material for outdoor polymer insulator based on IEC 61109. Four types of HTV silicone rubber sheet with different amount of ATH were tested continuously 1000
Abstract: The importance for manipulating an incorporated
scaffold and directing cell behaviors is well appreciated for tissue
engineering. Here, we developed newly nano-topographic oxidized
silicon nanosponges capable of being various chemical modifications
to provide much insight into the fundamental biology of how cells
interact with their surrounding environment in vitro. A wet etching
technique is exerted to allow us fabricated the silicon nanosponges in a
high-throughput manner. Furthermore, various organo-silane
chemicals enabled self-assembled on the surfaces by vapor deposition.
We have found that Chinese hamster ovary (CHO) cells displayed
certain distinguishable morphogenesis, adherent responses, and
biochemical properties while cultured on these chemical modified
nano-topographic structures in compared with the planar oxidized
silicon counterparts, indicating that cell behaviors can be influenced
by certain physical characteristic derived from nano-topography in
addition to the hydrophobicity of contact surfaces crucial for cell
adhesion and spreading. Of particular, there were predominant
nano-actin punches and slender protrusions formed while cells were
cultured on the nano-topographic structures. This study shed potential
applications of these nano-topographic biomaterials for controlling
cell development in tissue engineering or basic cell biology research.
Abstract: Each new semiconductor technology node
brings smaller transistors and wires. Although this makes
transistors faster, wires get slower. In nano-scale regime, the
standard copper (Cu) interconnect will become a major hurdle
for FPGA interconnect due to their high resistivity and
electromigration. This paper presents the comprehensive
evaluation of mixed CNT bundle interconnects and
investigates their prospects as energy efficient and high speed
interconnect for future FPGA routing architecture. All
HSPICE simulations are carried out at operating frequency of
1GHz and it is found that mixed CNT bundle implemented in
FPGAs as interconnect can potentially provide a substantial
delay and energy reduction over traditional interconnects at
32nm process technology.
Abstract: In this paper, design, fabrication and coupled
multifield analysis of hollow out-of-plane silicon microneedle array
with piezoelectrically actuated microfluidic device for transdermal
drug delivery (TDD) applications is presented. The fabrication
process of silicon microneedle array is first done by series of
combined isotropic and anisotropic etching processes using
inductively coupled plasma (ICP) etching technology. Then coupled
multifield analysis of MEMS based piezoelectrically actuated device
with integrated 2×2 silicon microneedle array is presented. To predict
the stress distribution and model fluid flow in coupled field analysis,
finite element (FE) and computational fluid dynamic (CFD) analysis
using ANSYS rather than analytical systems has been performed.
Static analysis and transient CFD analysis were performed to predict
the fluid flow through the microneedle array. The inlet pressure from
10 kPa to 150 kPa was considered for static CFD analysis. In the
lumen region fluid flow rate 3.2946 μL/min is obtained at 150 V for
2×2 microneedle array. In the present study the authors have
performed simulation of structural, piezoelectric and CFD analysis
on three dimensional model of the piezoelectrically actuated
mcirofluidic device integrated with 2×2 microneedle array.
Abstract: Governments around the world are expending
considerable time and resources framing strategies and policies to
deliver energy security. The term 'energy security' has quietly
slipped into the energy lexicon without any meaningful discourse
about its meaning or assumptions. An examination of explicit and
inferred definitions finds that the concept is inherently slippery
because it is polysemic in nature having multiple dimensions and
taking on different specificities depending on the country (or
continent), timeframe or energy source to which it is applied. But
what does this mean for policymakers? Can traditional policy
approaches be used to address the problem of energy security or does
its- polysemic qualities mean that it should be treated as a 'wicked'
problem? To answer this question, the paper assesses energy security
against nine commonly cited characteristics of wicked policy
problems and finds strong evidence of 'wickedness'.
Abstract: Virtual Reality Modelling Language (VRML) is description language, which belongs to a field Window on World virtual reality system. The file, which is in VRML format, can be interpreted by VRML explorer in three-dimensional scene. VRML was created with aim to represent virtual reality on Internet easier. Development of 3D graphic is connected with Silicon Graphic Corporation. VRML 2.0 is the file format for describing interactive 3D scenes and objects. It can be used in collaboration with www, can be used for 3D complex representations creating of scenes, products or VR applications VRML 2.0 enables represent static and animated objects too. Interesting application of VRML is in area of manufacturing systems presentation.
Abstract: In this paper, we propose a novel metal oxide
semiconductor field effect transistor with L-shaped channel structure
(LMOS), and several type of L-shaped structures are also designed,
studied and compared with the conventional MOSFET device for the
same average gate length (Lavg). The proposed device electrical
characteristics are analyzed and evaluated by three dimension (3-D)
ISE-TCAD simulator. It can be confirmed that the LMOS devices
have higher on-state drain current and both lower drain-induced
barrier lowering (DIBL) and subthreshold swing (S.S.) than its
conventional counterpart has. In addition, the transconductance and
voltage gain properties of the LMOS are also improved.
Abstract: An embedded system for SEU(single event upset) test
needs to be designed to prevent system failure by high-energy particles
during measuring SEU. SEU is a phenomenon in which the data is changed temporary in semiconductor device caused by high-energy particles. In this paper, we present an embedded system for
SRAM(static random access memory) SEU test. SRAMs are on the DUT(device under test) and it is separated from control board which
manages the DUT and measures the occurrence of SEU. It needs to
have considerations for preventing system failure while managing the
DUT and making an accurate measurement of SEUs. We measure the occurrence of SEUs from five different SRAMs at three different
cyclotron beam energies 30, 35, and 40MeV. The number of SEUs of SRAMs ranges from 3.75 to 261.00 in average.
Abstract: One way for optimum loading of overdimensioning
conveyers is speed (capacity) decrement, with attention for
production capabilities and demands. At conveyers which drives with
three phase slip-ring induction motor, technically reasonable solution
for conveyer (driving motors) speed regulation is using constant
torque subsynchronous cascade with static semiconductor converter
and transformer for energy reversion to the power network. In the
paper is described mathematical model for parameter calculation of
two-motors 6 kV subsynchronous cascade. It is also demonstrated
that applying of this cascade gave several good properties, foremost
in electrical energy saving, also in improving of other energy
indexes, and finally that results in cost reduction of complete
electrical motor drive.
Abstract: A hardware efficient, multi mode, re-configurable
architecture of interleaver/de-interleaver for multiple standards,
like DVB, WiMAX and WLAN is presented. The interleavers
consume a large part of silicon area when implemented by using
conventional methods as they use memories to store permutation
patterns. In addition, different types of interleavers in different
standards cannot share the hardware due to different construction
methodologies. The novelty of the work presented in this paper is
threefold: 1) Mapping of vital types of interleavers including
convolutional interleaver onto a single architecture with flexibility
to change interleaver size; 2) Hardware complexity for channel
interleaving in WiMAX is reduced by using 2-D realization of the
interleaver functions; and 3) Silicon cost overheads reduced by
avoiding the use of small memories. The proposed architecture
consumes 0.18mm2 silicon area for 0.12μm process and can
operate at a frequency of 140 MHz. The reduced complexity helps
in minimizing the memory utilization, and at the same time
provides strong support to on-the-fly computation of permutation
patterns.
Abstract: A simple and dexterous in situ method was introduced to load CdS nanocrystals into organofunctionalized mesoporous, which used an ion-exchange method. The products were extensively characterized by combined spectroscopic methods. X- ray diffraction (XRD) and high-resolution transmission electron microscopy (HRTEM) demonstrated both the maintenance of pore symmetry (space group p6mm) of SBA-15 and the presence of CdS nanocrystals with uniform sizes of about 6 - 8 nm inside the functionalized SBA-15 channels. These mesoporous silica-supported CdS composites showed room temperature photoluminescence properties with a blue shift, indicating the quantum size effect of nanocrystalline CdS.
Abstract: In the present simulation work, an attempt is made to study the switching dynamics of an optically controlled 4HSiC thyristor power semiconductor device with the use of GaAs optically triggered power transistor. The half-cell thyristor has the forward breakdown of 200 V and reverse breakdown of more than 1000 V. The optically controlled thyristor has a rise time of 0.14 μs and fall time of 0.065 μs. The turn-on and turn-off delays are 0.1 μs and 0.06 μs, respectively. In addition, this optically controlled thyristor is used as a control switch for the DC-DC Boost converter. The pn-diode used for the converter has the forward drop of 2.8 V and reverse breakdown of around 400 V.
Abstract: Wastages such as grated coconut meat, spent tea and used sugarcane had contributed negative impacts to the environment. Vermicomposting method is fully utilized to manage the wastes towards a more sustainable approach. The worms that are used in the vermicomposting are Eisenia foetida and Eudrillus euginae. This research shows that the vermicompost of wastages has voltage of electrical energy and is able to light up the Light-Emitting Diode (LED) device. Based on the experiment, the use of replicated and double compartments of the component will produce double of voltage. Hence, for conclusion, this harmless and low cost technology of vermicompost can act as a dry cell in order to reduce the usage of hazardous chemicals that can contaminate the environment.
Abstract: The study of the transport coefficients in electronic
devices is currently carried out by analytical and empirical models.
This study requires several simplifying assumptions, generally
necessary to lead to analytical expressions in order to study the
different characteristics of the electronic silicon-based devices.
Further progress in the development, design and optimization of
Silicon-based devices necessarily requires new theory and modeling
tools. In our study, we use the PSO (Particle Swarm Optimization)
technique as a computational tool to develop analytical approaches in
order to study the transport phenomenon of the electron in crystalline
silicon as function of temperature and doping concentration. Good
agreement between our results and measured data has been found.
The optimized analytical models can also be incorporated into the
circuits simulators to study Si-based devices without impact on the
computational time and data storage.
Abstract: In this study, the Taguchi method was used to optimize the effect of HALO structure or halo implant variations on threshold voltage (VTH) and leakage current (ILeak) in 45nm p-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) device. Besides halo implant dose, the other process parameters which used were Source/Drain (S/D) implant dose, oxide growth temperature and silicide anneal temperature. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, the most effective process parameters with respect to VTH and ILeak are halo implant dose (40%) and S/D implant dose (52%) respectively. Whereas the second ranking factor affecting VTH and ILeak are oxide growth temperature (32%) and halo implant dose (34%) respectively. The results show that after optimizations approaches is -0.157V at ILeak=0.195mA/μm.
Abstract: The direct implementation of interleaver functions
in WiMAX is not hardware efficient due to presence of complex
functions. Also the conventional method i.e. using memories for
storing the permutation tables is silicon consuming. This work
presents a 2-D transformation for WiMAX channel interleaver
functions which reduces the overall hardware complexity to
compute the interleaver addresses on the fly. A fully reconfigurable
architecture for address generation in WiMAX
channel interleaver is presented, which consume 1.1 k-gates in
total. It can be configured for any block size and any modulation
scheme in WiMAX. The presented architecture can run at a
frequency of 200 MHz, thus fully supporting high bandwidth
requirements for WiMAX.
Abstract: RF performance of SOI CMOS device has attracted
significant amount of interest recently. In order to improve RF
parameters, Strained Si/Relaxed Si0.8Ge0.2 investigated as a
replacement for Si technology .Enhancement of carrier mobility
associated with strain engineering makes Strained Si a promising
candidate for improving RF performance of CMOS technology.
From the simulation, the cut-off frequency is estimated to be 224
GHZ, whereas in SOI at similar bias is about 188 GHZ. Therefore,
Strained Si exhibits 19% improvement in cut-off frequency over
similar Si counterpart. In this paper, Ion/Ioff ratio is studied as one of
the key parameters in logic and digital application. Strained Si/SiGe
demonstrates better Ion/Ioff characteristic than SOI, in similar channel
length of 100 nm.Another important key analog figures of merit such
as Early Voltage (VEA) ,transconductance vs drain current (gm /Ids)
are studied. They introduce the efficiency of the devices to convert
dc power into ac frequency.
Abstract: In this work we numerically examine structures which
could confine light in nanometer areas. A system consisting of two silicon disks with in plane separation of a few tens of nanometers has
been studied first. The normalized unitless effective mode volume, Veff, has been calculated for the two lowest whispering gallery mode resonances. The effective mode volume is reduced significantly as the gap between the disks decreases. In addition, the effect of the substrate is also studied. In that case, Veff of approximately the same
value as the non-substrate case for a similar two disk system can be
obtained by using disks almost twice as thick. We also numerically examine a structure consisting of a circular slot waveguide which is formed into a silicon disk resonator. We show that the proposed structure could have high Q resonances thus raising the belief that it
is a very promising candidate for optical interconnects applications.
The study includes several numerical calculations for all the geometric parameters of the structure. It also includes numerical simulations of the coupling between a waveguide and the proposed
disk resonator leading to a very promising conclusion about its applicability.