Abstract: A hardware efficient, multi mode, re-configurable
architecture of interleaver/de-interleaver for multiple standards,
like DVB, WiMAX and WLAN is presented. The interleavers
consume a large part of silicon area when implemented by using
conventional methods as they use memories to store permutation
patterns. In addition, different types of interleavers in different
standards cannot share the hardware due to different construction
methodologies. The novelty of the work presented in this paper is
threefold: 1) Mapping of vital types of interleavers including
convolutional interleaver onto a single architecture with flexibility
to change interleaver size; 2) Hardware complexity for channel
interleaving in WiMAX is reduced by using 2-D realization of the
interleaver functions; and 3) Silicon cost overheads reduced by
avoiding the use of small memories. The proposed architecture
consumes 0.18mm2 silicon area for 0.12μm process and can
operate at a frequency of 140 MHz. The reduced complexity helps
in minimizing the memory utilization, and at the same time
provides strong support to on-the-fly computation of permutation
patterns.
Abstract: The direct implementation of interleaver functions
in WiMAX is not hardware efficient due to presence of complex
functions. Also the conventional method i.e. using memories for
storing the permutation tables is silicon consuming. This work
presents a 2-D transformation for WiMAX channel interleaver
functions which reduces the overall hardware complexity to
compute the interleaver addresses on the fly. A fully reconfigurable
architecture for address generation in WiMAX
channel interleaver is presented, which consume 1.1 k-gates in
total. It can be configured for any block size and any modulation
scheme in WiMAX. The presented architecture can run at a
frequency of 200 MHz, thus fully supporting high bandwidth
requirements for WiMAX.