Low Complexity Multi Mode Interleaver Core for WiMAX with Support for Convolutional Interleaving

A hardware efficient, multi mode, re-configurable architecture of interleaver/de-interleaver for multiple standards, like DVB, WiMAX and WLAN is presented. The interleavers consume a large part of silicon area when implemented by using conventional methods as they use memories to store permutation patterns. In addition, different types of interleavers in different standards cannot share the hardware due to different construction methodologies. The novelty of the work presented in this paper is threefold: 1) Mapping of vital types of interleavers including convolutional interleaver onto a single architecture with flexibility to change interleaver size; 2) Hardware complexity for channel interleaving in WiMAX is reduced by using 2-D realization of the interleaver functions; and 3) Silicon cost overheads reduced by avoiding the use of small memories. The proposed architecture consumes 0.18mm2 silicon area for 0.12μm process and can operate at a frequency of 140 MHz. The reduced complexity helps in minimizing the memory utilization, and at the same time provides strong support to on-the-fly computation of permutation patterns.

Authors:

• Rizwan Asghar
• Dake Liu

Keywords:

• Hardware interleaver implementation
• WiMAX
• DVB
• block interleaver
• convolutional interleaver
• hardwaremultiplexing.

References:

[1] IEEE 802.16e-2005: "IEEE Standard for local and metropolitan area
networks, Part 16: Air Interface for Fixed Broadband Wireless Access
Systems - Amendment 2: Medium Access Control Layers for
Combined Fixed and Mobile Operations in Licensed Bands."
[2] ETSI EN 300-744 V1.5.1: "Digital Video Broadcasting (DVB);
Framing Structure, Channel Coding and Modulation for Digital
Terrestrial Television," Nov. 2004.
[3] IEEE 802.11-2007: "Standard for local and metropolitan area
networks, Part 11: Wireless LAN Medium Access Control (MAC)
and Physical Layer (PHY) Sepcifications," Revision of IEEE Std.
802.11-1999.
[4] Y. N. Chang and Y. C. Ding: "A Low-Cost Dual Mode De-interleaver
Design," Int. conf. on Consumer Electronics, 2007.
[5] Y. N. Chang: "A Low-Cost Dual Mode De-interleaver Design," IEEE
Transaction on Consumer Electronics, vol. 54, no. 2, May 2008, pp.
326 - 332.
[6] Y. W. Wu and P. Ting: "A High Speed Interleaver for Emerging
Wireless Communications," Proc. of International Conf. on Wireless
Networks, Communications and Mobile Computing, vol. 2, June
2005, pp. 1192 - 1197.
[7] J. B. Kim, Y. J. Lim and M. H. Lee: "A low complexity FEC Design
for DAB," Proc. of IEEE Int. Symposium On Circuits and Systems,
May 2001, vol. 4, Sydney, Australia, pp. 522 - 525.
[8] G. D. Forney: "Burst-Correcting Codes for the Classic Bursty
Channel," IEEE Transaction on Communication Tech., Oct-1971,
Vol. COM-19, No. 5, pp. 772 - 781.
[9] J. L. Ramsey: "Realization of Optimum Interleavers," IEEE
Transaction on Information Theory, May-1970, Vol. IT-16, No. 3, pp.
338 - 345.
[10] C. Berrou, A. Glavieus, and P. Thitimajshima: "Near Shannon limit
error-correcting coding and decoding: Turbo-codes," Proc. of IEEE
ICC, May 1993, vol. 2, pp. 1064 - 1070.
[11] Ji-Hoon Kim and In-Cheol Park: "Duo-binary circular turbo decoder
based on border metric encoding for WiMAX," Proc. of IEEE
ASPDAC, March 2008, pp. 109 - 110.
[12] Cheng-Hung Lin, Chun-Yu Chen and An-Yeu Wu: "High-
Throughput 12-Mode CTC Decoder for WiMAX Standard," Proc. of
IEEE VLSI-DAT, April 2008, pp. 216 - 219.
[13] C. Berrou, M. Jezequel, C. Douillard, and S. Kerouedan: "The
advantages of non-binary Turbo codes," Proc. of IEEE Info. Theory
Workshop, Sept. 2001, pp. 61-63.
[14] S. Vafi and T. Wysocki: "Weight distribution of turbo codes with
convolution interleavers," IET Communications, 2007, Vol. 1(1), pp.
71 - 78.
[15] E. K. Hall and S. G. Wilson: "Stream-Oriented Turbo Codes," IEEE
Transaction on Information Theory, July-2001, Vol. 47, No. 5, pp.
1813 - 1831.
[16] S. Vafi and T. Wysocki: "On the Performance of Turbo Codes with
Convolutional Interleavers," Proc. of Asia-Pacific Conference on
Communications, Oct. 2005, pp. 222 - 226.
[17] S. Vafi and T. Wysocki: "Performance of convolutional interleavers
with different spacing parameters in turbo codes," Proc. of 6th
Australian Communication Theory Workshop, Feb. 2005, pp. 8 -12.
[18] Xilinx Inc.: "Interleaver/De-Interleaver," Product Specification, v5.1,
DS250, March 2008.
[19] Altera Inc.: "Symbol Interleaver/De-Interleaver Core," Mega Core
Function User-s Guide, ver. 1.3.0, June 2002.
[20] Lattice Semiconductor Inc.: "Interleaver/De-Interleaver IP Core,"
Core User-s Guide, ipug_61_02.5, August, 2008