2-D Realization of WiMAX Channel Interleaver for Efficient Hardware Implementation
The direct implementation of interleaver functions
in WiMAX is not hardware efficient due to presence of complex
functions. Also the conventional method i.e. using memories for
storing the permutation tables is silicon consuming. This work
presents a 2-D transformation for WiMAX channel interleaver
functions which reduces the overall hardware complexity to
compute the interleaver addresses on the fly. A fully reconfigurable
architecture for address generation in WiMAX
channel interleaver is presented, which consume 1.1 k-gates in
total. It can be configured for any block size and any modulation
scheme in WiMAX. The presented architecture can run at a
frequency of 200 MHz, thus fully supporting high bandwidth
requirements for WiMAX.
[1] IEEE 802.16e-2005: "IEEE Standard for local and metropolitan area
networks, Part 16: Air Interface for Fixed Broadband Wireless Access
Systems - Amendment 2: Medium Access Control Layers for
Combined Fixed and Mobile Operations in Licensed Bands."
[2] Y. N. Chang and Y. C. Ding: "A Low-Cost Dual Mode De-interleaver
Design," Int. conf. on Consumer Electronics, 2007.
[3] Y. N. Chang: "A Low-Cost Dual Mode De-interleaver Design," IEEE
Transaction on Consumer Electronics, vol. 54, no. 2, May 2008, pp.
326 - 332.
[4] Y. W. Wu and P. Ting: "A High Speed Interleaver for Emerging
Wireless Communications," Proc. of International Conf. on Wireless
Networks, Communications and Mobile Computing, vol. 2, June
2005, pp. 1192 - 1197.
[1] IEEE 802.16e-2005: "IEEE Standard for local and metropolitan area
networks, Part 16: Air Interface for Fixed Broadband Wireless Access
Systems - Amendment 2: Medium Access Control Layers for
Combined Fixed and Mobile Operations in Licensed Bands."
[2] Y. N. Chang and Y. C. Ding: "A Low-Cost Dual Mode De-interleaver
Design," Int. conf. on Consumer Electronics, 2007.
[3] Y. N. Chang: "A Low-Cost Dual Mode De-interleaver Design," IEEE
Transaction on Consumer Electronics, vol. 54, no. 2, May 2008, pp.
326 - 332.
[4] Y. W. Wu and P. Ting: "A High Speed Interleaver for Emerging
Wireless Communications," Proc. of International Conf. on Wireless
Networks, Communications and Mobile Computing, vol. 2, June
2005, pp. 1192 - 1197.
@article{"International Journal of Electrical, Electronic and Communication Sciences:56311", author = "Rizwan Asghar and Dake Liu", title = "2-D Realization of WiMAX Channel Interleaver for Efficient Hardware Implementation", abstract = "The direct implementation of interleaver functions
in WiMAX is not hardware efficient due to presence of complex
functions. Also the conventional method i.e. using memories for
storing the permutation tables is silicon consuming. This work
presents a 2-D transformation for WiMAX channel interleaver
functions which reduces the overall hardware complexity to
compute the interleaver addresses on the fly. A fully reconfigurable
architecture for address generation in WiMAX
channel interleaver is presented, which consume 1.1 k-gates in
total. It can be configured for any block size and any modulation
scheme in WiMAX. The presented architecture can run at a
frequency of 200 MHz, thus fully supporting high bandwidth
requirements for WiMAX.", keywords = "Interleaver, deinterleaver, WiMAX, 802.16e.", volume = "3", number = "3", pages = "486-5", }