Optimization of HALO Structure Effects in 45nm p-type MOSFETs Device Using Taguchi Method
In this study, the Taguchi method was used to optimize the effect of HALO structure or halo implant variations on threshold voltage (VTH) and leakage current (ILeak) in 45nm p-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) device. Besides halo implant dose, the other process parameters which used were Source/Drain (S/D) implant dose, oxide growth temperature and silicide anneal temperature. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, the most effective process parameters with respect to VTH and ILeak are halo implant dose (40%) and S/D implant dose (52%) respectively. Whereas the second ranking factor affecting VTH and ILeak are oxide growth temperature (32%) and halo implant dose (34%) respectively. The results show that after optimizations approaches is -0.157V at ILeak=0.195mA/μm.
[1] Wong et. al., "CMOS scaling into the 21st Century: 0.1um and Beyond,"
IBM J. Res. & Dev. 39, 112. 1995.
[2] Kang, Sung-Mo, Leblebici, Yusuf, "CMOS digital integrated circuit:
analysis and design," 3th Edition. New York: McGraw-Hill Higher
Companies, Inc., 2003.
[3] S.M.Sze, "Semiconductor Devices: Physics and Technology," 2nd
Edition, John Wiley & Sons Inc., 1986.
[4] S.Ninomiya et al., "Vth Control by Halo Implantation using the SEN's
MIND System," in Proc. 9th International Workshop on Junction
Technology, 2009, pp. 100-103.
[5] Croon, J.A., Augendre, E., Decoutere, S., Sansen, W., Maes, H.E.,
"Influence of Doping Profile and Halo Implantation on the Threshold
Voltage Mismatch of a 0.13╬╝m CMOS Technology," in Proc. 32th
European Solid-State Device Research Conference (ESSDERC), Italy,
2002, pp. 579-582.
[6] Axel Erlebach, Thomas Feudal, Adreas Schenk, Christoph Zechner,
"Influence of HALO and drain-extension doping gradients on transistor
performance," J. Materials Science and Engineering B, 114-115, 2004,
pp. 15-19.
[7] Madhav S.Phadke, "Quality Engineering Using Robust Design,"
Pearson Education, Inc. and Dorling Kindersley Publishing, Inc., 1998.
[8] Ugur Esme. 2009. Application of Taguchi Method for the Optimization
of Resistance Spot Welding Process, The Arabian Journal for Science
and Engineering, Vol. 34, No. 2B
[9] G.P.Syros, J. Materials Processing Technology 135, (2003), 68-74
[10] N.V.R.Naidu, "Mathematical model for quality cost optimization,
Robotics and Computer-integrated Manufacturing," in Proc.
International Conference on Flexible Automation and Intelligent
Manufacturing, 2008, pp. 811-815.
[11] Kai Yang, Ee-Chon Teo and Franz Konstantin Fuss, "Application of
Taguchi method in optimization of cervical ring cage," J. Biomechanics,
Vol. 40, 2007, pp. 3251-3256.
[12] H.Abdullah, J.Jurait, A.Lennie, Z.M.Nopiah and I.Ahmad, "Simulation
of Fabrication Process VDMOSFET Transistor Using Silvaco
Software," European J. Scientific Research, ISSN 1450-216X, Vol.29
No.4, 2009, pp. 461-470.
[13] Ashok K. Goel, Matthew Merry, Kathryn Arkenberg, Eric Therkidsen,
EmanuelChiaburu, William Standfest, "Optimization of Device
Performance Using Semiconductor TCAD Tools," Silvaco International,
Product Description, Silvaco International, 2001.
[14] Belal Ahmed Hamida, Ibrahim Ahmad. 2007. "Optimization of PMOS
65nm Using Taguchi Method," in Proc. International Conference on
Modeling and Simulation, Coimbatore, 2007, August 27-29.
[15] ITRS Report (2007); http://www.itrs.net
[16] N.V.R.Naidu, "Mathematical model for quality cost optimization,
Robotics and Computer-integrated Manufacturing," in Proc.
International Conference on Flexible Automation and Intelligent
Manufacturing, 2008, pp. 811-815.
[17] M.Nalbant, H.Gokkaya, G.Sur, "Application of Taguchi method in the
optimization of cutting parameters for surface roughness turning," J.
Materials and Design, Vol. 28, 2007, pp. 1379-1385.
[1] Wong et. al., "CMOS scaling into the 21st Century: 0.1um and Beyond,"
IBM J. Res. & Dev. 39, 112. 1995.
[2] Kang, Sung-Mo, Leblebici, Yusuf, "CMOS digital integrated circuit:
analysis and design," 3th Edition. New York: McGraw-Hill Higher
Companies, Inc., 2003.
[3] S.M.Sze, "Semiconductor Devices: Physics and Technology," 2nd
Edition, John Wiley & Sons Inc., 1986.
[4] S.Ninomiya et al., "Vth Control by Halo Implantation using the SEN's
MIND System," in Proc. 9th International Workshop on Junction
Technology, 2009, pp. 100-103.
[5] Croon, J.A., Augendre, E., Decoutere, S., Sansen, W., Maes, H.E.,
"Influence of Doping Profile and Halo Implantation on the Threshold
Voltage Mismatch of a 0.13╬╝m CMOS Technology," in Proc. 32th
European Solid-State Device Research Conference (ESSDERC), Italy,
2002, pp. 579-582.
[6] Axel Erlebach, Thomas Feudal, Adreas Schenk, Christoph Zechner,
"Influence of HALO and drain-extension doping gradients on transistor
performance," J. Materials Science and Engineering B, 114-115, 2004,
pp. 15-19.
[7] Madhav S.Phadke, "Quality Engineering Using Robust Design,"
Pearson Education, Inc. and Dorling Kindersley Publishing, Inc., 1998.
[8] Ugur Esme. 2009. Application of Taguchi Method for the Optimization
of Resistance Spot Welding Process, The Arabian Journal for Science
and Engineering, Vol. 34, No. 2B
[9] G.P.Syros, J. Materials Processing Technology 135, (2003), 68-74
[10] N.V.R.Naidu, "Mathematical model for quality cost optimization,
Robotics and Computer-integrated Manufacturing," in Proc.
International Conference on Flexible Automation and Intelligent
Manufacturing, 2008, pp. 811-815.
[11] Kai Yang, Ee-Chon Teo and Franz Konstantin Fuss, "Application of
Taguchi method in optimization of cervical ring cage," J. Biomechanics,
Vol. 40, 2007, pp. 3251-3256.
[12] H.Abdullah, J.Jurait, A.Lennie, Z.M.Nopiah and I.Ahmad, "Simulation
of Fabrication Process VDMOSFET Transistor Using Silvaco
Software," European J. Scientific Research, ISSN 1450-216X, Vol.29
No.4, 2009, pp. 461-470.
[13] Ashok K. Goel, Matthew Merry, Kathryn Arkenberg, Eric Therkidsen,
EmanuelChiaburu, William Standfest, "Optimization of Device
Performance Using Semiconductor TCAD Tools," Silvaco International,
Product Description, Silvaco International, 2001.
[14] Belal Ahmed Hamida, Ibrahim Ahmad. 2007. "Optimization of PMOS
65nm Using Taguchi Method," in Proc. International Conference on
Modeling and Simulation, Coimbatore, 2007, August 27-29.
[15] ITRS Report (2007); http://www.itrs.net
[16] N.V.R.Naidu, "Mathematical model for quality cost optimization,
Robotics and Computer-integrated Manufacturing," in Proc.
International Conference on Flexible Automation and Intelligent
Manufacturing, 2008, pp. 811-815.
[17] M.Nalbant, H.Gokkaya, G.Sur, "Application of Taguchi method in the
optimization of cutting parameters for surface roughness turning," J.
Materials and Design, Vol. 28, 2007, pp. 1379-1385.
@article{"International Journal of Electrical, Electronic and Communication Sciences:56344", author = "F. Salehuddin and I. Ahmad and F. A. Hamid and A. Zaharim and H. A. Elgomati and B. Y. Majlis and P. R. Apte", title = "Optimization of HALO Structure Effects in 45nm p-type MOSFETs Device Using Taguchi Method", abstract = "In this study, the Taguchi method was used to optimize the effect of HALO structure or halo implant variations on threshold voltage (VTH) and leakage current (ILeak) in 45nm p-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) device. Besides halo implant dose, the other process parameters which used were Source/Drain (S/D) implant dose, oxide growth temperature and silicide anneal temperature. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, the most effective process parameters with respect to VTH and ILeak are halo implant dose (40%) and S/D implant dose (52%) respectively. Whereas the second ranking factor affecting VTH and ILeak are oxide growth temperature (32%) and halo implant dose (34%) respectively. The results show that after optimizations approaches is -0.157V at ILeak=0.195mA/μm.
", keywords = "Optimization, p-type MOSFETs device, HALO Structure, Taguchi Method.", volume = "5", number = "3", pages = "346-7", }
