Abstract: A reconfigurable manufacturing system (RMS) is an
advanced system designed at the outset for rapid changes in its hardware
and software components in order to quickly adjust its production
capacity and functionally. Among various operational decisions, this
study considers the scheduling problem that determines the input
sequence and schedule at the same time for a given set of parts. In
particular, we consider the practical constraints that the numbers of
pallets/fixtures are limited and hence a part can be released into the
system only when the fixture required for the part is available. To
solve the integrated input sequencing and scheduling problems, we
suggest a priority rule based approach in which the two sub-problems
are solved using a combination of priority rules. To show the effectiveness
of various rule combinations, a simulation experiment was
done on the data for a real RMS, and the test results are reported.
Abstract: Code mobility technologies attract more and more developers and consumers. Numerous domains are concerned, many platforms are developed and interest applications are realized. However, developing good software products requires modeling, analyzing and proving steps. The choice of models and modeling languages is so critical on these steps. Formal tools are powerful in analyzing and proving steps. However, poorness of classical modeling language to model mobility requires proposition of new models. The objective of this paper is to provide a specific formalism “Coloured Reconfigurable Nets" and to show how this one seems to be adequate to model different kinds of code mobility.
Abstract: The evolution of logic circuits, which falls under the heading of evolvable hardware, is carried out by evolutionary algorithms. These algorithms are able to automatically configure reconfigurable devices. One of main difficulties in developing evolvable hardware with the ability to design functional electrical circuits is to choose the most favourable EA features such as fitness function, chromosome representations, population size, genetic operators and individual selection. Until now several researchers from the evolvable hardware community have used and tuned these parameters and various rules on how to select the value of a particular parameter have been proposed. However, to date, no one has presented a study regarding the size of the chromosome representation (circuit layout) to be used as a platform for the evolution in order to increase the evolvability, reduce the number of generations and optimize the digital logic circuits through reducing the number of logic gates. In this paper this topic has been thoroughly investigated and the optimal parameters for these EA features have been proposed. The evolution of logic circuits has been carried out by an extrinsic evolvable hardware system which uses (1+λ) evolution strategy as the core of the evolution.
Abstract: .Hardware realization of a Neural Network (NN), to a large extent depends on the efficient implementation of a single neuron. FPGA-based reconfigurable computing architectures are suitable for hardware implementation of neural networks. FPGA realization of ANNs with a large number of neurons is still a challenging task. This paper discusses the issues involved in implementation of a multi-input neuron with linear/nonlinear excitation functions using FPGA. Implementation method with resource/speed tradeoff is proposed to handle signed decimal numbers. The VHDL coding developed is tested using Xilinx XC V50hq240 Chip. To improve the speed of operation a lookup table method is used. The problems involved in using a lookup table (LUT) for a nonlinear function is discussed. The percentage saving in resource and the improvement in speed with an LUT for a neuron is reported. An attempt is also made to derive a generalized formula for a multi-input neuron that facilitates to estimate approximately the total resource requirement and speed achievable for a given multilayer neural network. This facilitates the designer to choose the FPGA capacity for a given application. Using the proposed method of implementation a neural network based application, namely, a Space vector modulator for a vector-controlled drive is presented
Abstract: In this research paper, a slotted coaxial line fed cross
dipole excitation structure for short backfire antenna is proposed and
developed to achieve reconfigurable circular polarization. The cross
dipole, which is fed by the slotted coaxial line, consists of two
orthogonal dipoles. The dipoles are mounted on the outer conductor
of the coaxial line. A unique technique is developed to generate
reconfigurable circular polarization using cross dipole configuration.
The sub-reflector is supported by the feed line, thus requiring no
extra support. The antenna is developed on elliptical ground plane
with dielectric rim making antenna compact. It is demonstrated that
cross dipole excited short backfire antenna can achieve voltage
standing wave ratio (VSWR) bandwidth of 14.28% for 2:1 VSWR,
axial ratio of 0.2 dB with axial ratio (≤ 3dB) bandwidth of 2.14% and
a gain of more than 12 dBi. The experimental results for the designed
antenna structure are in close agreement with computer simulations.
Abstract: Banyan networks are really attractive for serving as
the optical switching architectures due to their unique properties of
small depth and absolute signal loss uniformity. The fact has been
established that the limitations of blocking nature and the nonavailability
of proper connections due to non-rearrangeable property
can be easily ruled out using electro-optic MZI switches as basic
switching elements. Combination of the horizontal expansion and
vertical stacking of optical banyan networks is an appropriate scheme
for constructing non-blocking banyan-based optical switching
networks. The interconnected banyan switching fabrics (IBSF) have
been considered and analyzed to best serve the purpose of optical
switching with electro-optic MZI basic elements. The cross/bar state
interchange for the switches has been facilitated by appropriate
voltage switching or the by the switching of operating wavelength.
The paper is dedicated to the modification of the basic switching
element being used as well as the architecture of the switching
network.
Abstract: This paper proposes a low-voltage and low-power
fully integrated digitally tuned continuous-time channel selection
filter for WiMAX applications. A 5th-order elliptic low-pass filter is
realized in a Gm-C topology. The bandwidth of the fully differential
filter is reconfigurable from 2.5MHz to 20MHz (8x) for different
requirements in WiMAX applications. The filter is simulated in a
standard 90nm CMOS process. Simulation results show the THD
(@Vout =100mVpp) is less than -66dB. The in-band ripple of the
filter is about 0.15dB. The filter consumes 1.5mW from a supply
voltage of 0.9V.
Abstract: This paper describes about dynamic reconfiguration to
miniaturize arithmetic circuits in general-purpose processor. Dynamic
reconfiguration is a technique to realize required functions by
changing hardware construction during operation. The proposed
arithmetic circuit performs floating-point arithmetic which is
frequently used in science and technology. The data format is
floating-point based on IEEE754. The proposed circuit is designed
using VHDL, and verified the correct operation by simulations and
experiments.
Abstract: The purpose of the paper is to develop an informationcontrol environment for overall management and self-reconfiguration of the reconfigurable multifunctional machine tool for machining both rotation and prismatic parts and high concentration of different technological operations - turning, milling, drilling, grinding, etc. For the realization of this purpose on the basis of defined sub-processes for the implementation of the technological process, architecture of the information-search system for machine control is suggested. By using the object-oriented method, a structure and organization of the search system based on agents and manager with central control are developed. Thus conditions for identification of available information in DBs, self-reconfiguration of technological system and entire control of the reconfigurable multifunctional machine tool are created.
Abstract: Manufacturing Industries face a crucial change as products and processes are required to, easily and efficiently, be reconfigurable and reusable. In order to stay competitive and flexible, situations also demand distribution of enterprises globally, which requires implementation of efficient communication strategies. A prototype system called the “Broadcaster" has been developed with an assumption that the control environment description has been engineered using the Component-based system paradigm. This prototype distributes information to a number of globally distributed partners via an adoption of the circular-based data processing mechanism. The work highlighted in this paper includes the implementation of this mechanism in the domain of the manufacturing industry. The proposed solution enables real-time remote propagation of machine information to a number of distributed supply chain client resources such as a HMI, VRML-based 3D views and remote client instances regardless of their distribution nature and/ or their mechanisms. This approach is presented together with a set of evaluation results. Authors- main concentration surrounds the reliability and the performance metric of the adopted approach. Performance evaluation is carried out in terms of the response times taken to process the data in this domain and compared with an alternative data processing implementation such as the linear queue mechanism. Based on the evaluation results obtained, authors justify the benefits achieved from this proposed implementation and highlight any further research work that is to be carried out.
Abstract: The aim of this study is to identify the conditions of
implementation for reconfigurability in summarizing past flexible
manufacturing systems (FMS) research by drawing overall
conclusions from many separate High Performance Manufacturing
(HPM) studies. Meta-analysis will be applied to links between HPM
programs and their practices related to FMS and manufacturing
performance with particular reference to responsiveness performance.
More specifically, an application of meta-analysis will be made with
reference to two of the main steps towards the development of an
empirically-tested theory: testing the adequacy of the measurement of
variables and testing the linkages between the variables.
Abstract: A digital system is proposed for low power 100-
channel neural recording system in this paper, which consists of 100
amplifiers, 100 analog-to-digital converters (ADC), digital controller
and baseband, transceiver for data link and RF command link. The
proposed system is designed in a 0.18 μm CMOS process and 65 nm
CMOS process.
Abstract: Increasing the demand for effectively use of the
production facility requires the tools for sharing the manufacturing
facility through remote operation of the machining process. This
research introduces the methodology of machining technology for
direct remote operation of networked milling machine. The
integrated tools with virtual simulation, remote desktop protocol and
Setup Free Attachment for remote operation of milling process are
proposed. Accessing and monitoring of machining operation is
performed by remote desktop interface and 3D virtual simulations.
Capability of remote operation is supported by an auto setup
attachment with a reconfigurable pin type setup free technology
installed on the table of CNC milling machine to perform unattended
machining process. The system is designed using a computer server
and connected to a PC based controlled CNC machine for real time
monitoring. A client will access the server through internet
communication and virtually simulate the machine activity. The
result has been presented that combination between real time virtual
simulation and remote desktop tool is enabling to operate all machine
tool functions and as well as workpiece setup..
Abstract: This paper proposes an architecture of dynamically
reconfigurable arithmetic circuit. Dynamic reconfiguration is a
technique to realize required functions by changing hardware
construction during operations. The proposed circuit is based on a
complex number multiply-accumulation circuit which is used
frequently in the field of digital signal processing. In addition, the
proposed circuit performs real number double precision arithmetic
operations. The data formats are single and double precision floating
point number based on IEEE754. The proposed circuit is designed
using VHDL, and verified the correct operation by simulations and
experiments.
Abstract: The direct implementation of interleaver functions
in WiMAX is not hardware efficient due to presence of complex
functions. Also the conventional method i.e. using memories for
storing the permutation tables is silicon consuming. This work
presents a 2-D transformation for WiMAX channel interleaver
functions which reduces the overall hardware complexity to
compute the interleaver addresses on the fly. A fully reconfigurable
architecture for address generation in WiMAX
channel interleaver is presented, which consume 1.1 k-gates in
total. It can be configured for any block size and any modulation
scheme in WiMAX. The presented architecture can run at a
frequency of 200 MHz, thus fully supporting high bandwidth
requirements for WiMAX.
Abstract: One of the main research directions in CAD/CAM
machining area is the reducing of machining time.
The feedrate scheduling is one of the advanced techniques that
allows keeping constant the uncut chip area and as sequel to keep
constant the main cutting force. They are two main ways for feedrate
optimization. The first consists in the cutting force monitoring, which
presumes to use complex equipment for the force measurement and
after this, to set the feedrate regarding the cutting force variation. The
second way is to optimize the feedrate by keeping constant the
material removal rate regarding the cutting conditions.
In this paper there is proposed a new approach using an extended
database that replaces the system model.
The feedrate scheduling is determined based on the identification
of the reconfigurable machine tool, and the feed value determination
regarding the uncut chip section area, the contact length between tool
and blank and also regarding the geometrical roughness.
The first stage consists in the blank and tool monitoring for the
determination of actual profiles. The next stage is the determination
of programmed tool path that allows obtaining the piece target
profile.
The graphic representation environment models the tool and blank
regions and, after this, the tool model is positioned regarding the
blank model according to the programmed tool path. For each of
these positions the geometrical roughness value, the uncut chip area
and the contact length between tool and blank are calculated. Each of
these parameters are compared with the admissible values and
according to the result the feed value is established.
We can consider that this approach has the following advantages:
in case of complex cutting processes the prediction of cutting force is
possible; there is considered the real cutting profile which has
deviations from the theoretical profile; the blank-tool contact length
limitation is possible; it is possible to correct the programmed tool
path so that the target profile can be obtained.
Applying this method, there are obtained data sets which allow the
feedrate scheduling so that the uncut chip area is constant and, as a
result, the cutting force is constant, which allows to use more
efficiently the machine tool and to obtain the reduction of machining
time.
Abstract: Fixed-point simulation results are used for the performance measure of inverting matrices using a reconfigurable processing element. Matrices are inverted using the Cholesky decomposition algorithm. The reconfigurable processing element is capable of all required mathematical operations. The fixed-point word length analysis is based on simulations of different condition numbers and different matrix sizes.
Abstract: Reconfigurable optical add/drop multiplexers
(ROADMs) can be classified into three categories based on their
underlying switching technologies. Category I consists of a single
large optical switch; category II is composed of a number of small
optical switches aligned in parallel; and category III has a single
optical switch and only one wavelength being added/dropped. In this
paper, to evaluate the wavelength-routing capability of ROADMs of
category-II in dynamic optical networks,the dynamic traffic models
are designed based on Bernoulli, Poisson distributions for smooth
and regular types of traffic. Through Analytical and Simulation
results, the routing power of cat-II of ROADM networks for two
traffic models are determined.
Abstract: Fully customized hardware based technology provides high performance and low power consumption by specializing the tasks in hardware but lacks design flexibility since any kind of changes require re-design and re-fabrication. Software based solutions operate with software instructions due to which a great flexibility is achieved from the easy development and maintenance of the software code. But this execution of instructions introduces a high overhead in performance and area consumption. In past few decades the reconfigurable computing domain has been introduced which overcomes the traditional trades-off between flexibility and performance and is able to achieve high performance while maintaining a good flexibility. The dramatic gains in terms of chip performance and design flexibility achieved through the reconfigurable computing systems are greatly dependent on the design of their computational units being integrated with reconfigurable logic resources. The computational unit of any reconfigurable system plays vital role in defining its strength. In this research paper an RFU based computational unit design has been presented using the tightly coupled, multi-threaded reconfigurable cores. The proposed design has been simulated for VLIW based architectures and a high gain in performance has been observed as compared to the conventional computing systems.
Abstract: This paper explains a project based learning method where autonomous mini-robots are developed for research, education and entertainment purposes. In case of remote systems wireless sensors are developed in critical areas, which would collect data at specific time intervals, send the data to the central wireless node based on certain preferred information would make decisions to turn on or off a switch or control unit. Such information transfers hardly sums up to a few bytes and hence low data rates would suffice for such implementations. As a robot is a multidisciplinary platform, the interfacing issues involved are discussed in this paper. The paper is mainly focused on power supply, grounding and decoupling issues.