A Dynamically Reconfigurable Arithmetic Circuit for Complex Number and Double Precision Number
This paper proposes an architecture of dynamically
reconfigurable arithmetic circuit. Dynamic reconfiguration is a
technique to realize required functions by changing hardware
construction during operations. The proposed circuit is based on a
complex number multiply-accumulation circuit which is used
frequently in the field of digital signal processing. In addition, the
proposed circuit performs real number double precision arithmetic
operations. The data formats are single and double precision floating
point number based on IEEE754. The proposed circuit is designed
using VHDL, and verified the correct operation by simulations and
experiments.
[1] T. J. Todman, G. A. Constantinides, S. J. E. Wilton, O. Mencer, W. Luk
and P. Y. K. Cheung, "Reconfigurable computing: architectures and
design methods", IEE Proc.-Computers & Digital Techniques, vol. 152,
no. 2, pp. 193 - 207, 2005.
[2] T. Sato, H. Watanabe, K. Shiba, "Implementation of dynamically
reconfigurable processor DAPDNA-2", VLSI Design, Automation and
Test, 2005 IEEE VLSI-TSA International Symposium, pp. 323-324, 2005.
[3] M J. Myjak, J. G. Delgado-Frias, "A Medium-Grain Reconfigurable
Architecture for DSP: VLSI Design, Benchmark Mapping, and
Performance", IEEE Trans. on VLSI Systems, vol.16, no.1, pp.14-23, Jan
2008.
[4] Monte Tull, et al., "High-Speed Complex Number Multiplier and
Inner-Product Processor", IEEE Trans. on Circuits and Systems, vol. 3,
pp.III-640 - III-643, Aug. 2002.
[5] Xilinx, Inc., ML401/ML402/ML403 Evaluation Platform User Guide
UG080 (v2.5), May 2006
[6] Xilinx, Inc., MicroBlaze Processor Reference Guide UG081 (v9.0), 2008.
[1] T. J. Todman, G. A. Constantinides, S. J. E. Wilton, O. Mencer, W. Luk
and P. Y. K. Cheung, "Reconfigurable computing: architectures and
design methods", IEE Proc.-Computers & Digital Techniques, vol. 152,
no. 2, pp. 193 - 207, 2005.
[2] T. Sato, H. Watanabe, K. Shiba, "Implementation of dynamically
reconfigurable processor DAPDNA-2", VLSI Design, Automation and
Test, 2005 IEEE VLSI-TSA International Symposium, pp. 323-324, 2005.
[3] M J. Myjak, J. G. Delgado-Frias, "A Medium-Grain Reconfigurable
Architecture for DSP: VLSI Design, Benchmark Mapping, and
Performance", IEEE Trans. on VLSI Systems, vol.16, no.1, pp.14-23, Jan
2008.
[4] Monte Tull, et al., "High-Speed Complex Number Multiplier and
Inner-Product Processor", IEEE Trans. on Circuits and Systems, vol. 3,
pp.III-640 - III-643, Aug. 2002.
[5] Xilinx, Inc., ML401/ML402/ML403 Evaluation Platform User Guide
UG080 (v2.5), May 2006
[6] Xilinx, Inc., MicroBlaze Processor Reference Guide UG081 (v9.0), 2008.
@article{"International Journal of Electrical, Electronic and Communication Sciences:57932", author = "Haruo Shimada and Akinori Kanasugi", title = "A Dynamically Reconfigurable Arithmetic Circuit for Complex Number and Double Precision Number", abstract = "This paper proposes an architecture of dynamically
reconfigurable arithmetic circuit. Dynamic reconfiguration is a
technique to realize required functions by changing hardware
construction during operations. The proposed circuit is based on a
complex number multiply-accumulation circuit which is used
frequently in the field of digital signal processing. In addition, the
proposed circuit performs real number double precision arithmetic
operations. The data formats are single and double precision floating
point number based on IEEE754. The proposed circuit is designed
using VHDL, and verified the correct operation by simulations and
experiments.", keywords = "arithmetic circuit, complex number, double precision,dynamic reconfiguration", volume = "3", number = "6", pages = "1349-7", }