Abstract: This paper describes about dynamic reconfiguration to
miniaturize arithmetic circuits in general-purpose processor. Dynamic
reconfiguration is a technique to realize required functions by
changing hardware construction during operation. The proposed
arithmetic circuit performs floating-point arithmetic which is
frequently used in science and technology. The data format is
floating-point based on IEEE754. The proposed circuit is designed
using VHDL, and verified the correct operation by simulations and
experiments.
Abstract: A special case of floating point data representation is block
floating point format where a block of operands are forced to have a joint
exponent term. This paper deals with the finite wordlength properties of
this data format. The theoretical errors associated with the error model for
block floating point quantization process is investigated with the help of error
distribution functions. A fast and easy approximation formula for calculating
signal-to-noise ratio in quantization to block floating point format is derived.
This representation is found to be a useful compromise between fixed point
and floating point format due to its acceptable numerical error properties over
a wide dynamic range.