Abstract: This paper proposes a novel solution for optimizing
the size and communication overhead of a distributed multiagent
system without compromising the performance. The proposed approach
addresses the challenges of scalability especially when the
multiagent system is large. A modified spectral clustering technique
is used to partition a large network into logically related clusters.
Agents are assigned to monitor dedicated clusters rather than monitor
each device or node. The proposed scalable multiagent system is
implemented using JADE (Java Agent Development Environment)
for a large power system. The performance of the proposed topologyindependent
decentralized multiagent system and the scalable multiagent
system is compared by comprehensively simulating different
fault scenarios. The time taken for reconfiguration, the overall computational
complexity, and the communication overhead incurred are
computed. The results of these simulations show that the proposed
scalable multiagent system uses fewer agents efficiently, makes faster
decisions to reconfigure when a fault occurs, and incurs significantly
less communication overhead.
Abstract: This paper presents methodologies for developing an
intelligent CAD system assisting in analysis and design of
reconfigurable special machines. It describes a procedure for
determining feasibility of utilizing these machines for a given part
and presents a model for developing an intelligent CAD system. The
system analyzes geometrical and topological information of the given
part to determine possibility of the part being produced by
reconfigurable special machines from a technical point of view. Also
feasibility of the process from a economical point of view is
analyzed. Then the system determines proper positioning of the part
considering details of machining features and operations needed.
This involves determination of operation types, cutting tools and the
number of working stations needed. Upon completion of this stage
the overall layout of the machine and machining equipment required
are determined.
Abstract: This paper reviews various approaches that have been
used for the modeling and simulation of large-scale engineering
systems and determines their appropriateness in the development of a
RICS modeling and simulation tool. Bond graphs, linear graphs,
block diagrams, differential and difference equations, modeling
languages, cellular automata and agents are reviewed. This tool
should be based on linear graph representation and supports symbolic
programming, functional programming, the development of noncausal
models and the incorporation of decentralized approaches.
Abstract: Fixed-point simulation results are used for the
performance measure of inverting matrices by Cholesky
decomposition. The fixed-point Cholesky decomposition algorithm
is implemented using a fixed-point reconfigurable processing
element. The reconfigurable processing element provides all
mathematical operations required by Cholesky decomposition. The
fixed-point word length analysis is based on simulations using
different condition numbers and different matrix sizes. Simulation
results show that 16 bits word length gives sufficient performance
for small matrices with low condition number. Larger matrices and
higher condition numbers require more dynamic range for a fixedpoint
implementation.
Abstract: Speedups from mapping four real-life DSP
applications on an embedded system-on-chip that couples coarsegrained
reconfigurable logic with an instruction-set processor are
presented. The reconfigurable logic is realized by a 2-Dimensional
Array of Processing Elements. A design flow for improving
application-s performance is proposed. Critical software parts, called
kernels, are accelerated on the Coarse-Grained Reconfigurable
Array. The kernels are detected by profiling the source code. For
mapping the detected kernels on the reconfigurable logic a prioritybased
mapping algorithm has been developed. Two 4x4 array
architectures, which differ in their interconnection structure among
the Processing Elements, are considered. The experiments for eight
different instances of a generic system show that important overall
application speedups have been reported for the four applications.
The performance improvements range from 1.86 to 3.67, with an
average value of 2.53, compared with an all-software execution.
These speedups are quite close to the maximum theoretical speedups
imposed by Amdahl-s law.
Abstract: A trend in agent community or enterprises is that they are shifting from closed to open architectures composed of a large number of autonomous agents. One of its implications could be that interface agent framework is getting more important in multi-agent system (MAS); so that systems constructed for different application domains could share a common understanding in human computer interface (HCI) methods, as well as human-agent and agent-agent interfaces. However, interface agent framework usually receives less attention than other aspects of MAS. In this paper, we will propose an interface web agent framework which is based on our former project called WAF and a Distributed HCI template. A group of new functionalities and implications will be discussed, such as web agent presentation, off-line agent reference, reconfigurable activation map of agents, etc. Their enabling techniques and current standards (e.g. existing ontological framework) are also suggested and shown by examples from our own implementation in WAF.
Abstract: Image convolution similar to the receptive fields
found in mammalian visual pathways has long been used in
conventional image processing in the form of Gabor masks.
However, no VLSI implementation of parallel, multi-layered pulsed
processing has been brought forward which would emulate this
property. We present a technical realization of such a pulsed image
processing scheme. The discussed IC also serves as a general testbed
for VLSI-based pulsed information processing, which is of interest
especially with regard to the robustness of representing an analog
signal in the phase or duration of a pulsed, quasi-digital signal, as
well as the possibility of direct digital manipulation of such an
analog signal. The network connectivity and processing properties
are reconfigurable so as to allow adaptation to various processing
tasks.
Abstract: Local Linear Neuro-Fuzzy Models (LLNFM) like other neuro- fuzzy systems are adaptive networks and provide robust learning capabilities and are widely utilized in various applications such as pattern recognition, system identification, image processing and prediction. Local linear model tree (LOLIMOT) is a type of Takagi-Sugeno-Kang neuro fuzzy algorithm which has proven its efficiency compared with other neuro fuzzy networks in learning the nonlinear systems and pattern recognition. In this paper, a dedicated reconfigurable and parallel processing hardware for LOLIMOT algorithm and its applications are presented. This hardware realizes on-chip learning which gives it the capability to work as a standalone device in a system. The synthesis results on FPGA platforms show its potential to improve the speed at least 250 of times faster than software implemented algorithms.
Abstract: Modern applications realized onto FPGAs exhibit high connectivity demands. Throughout this paper we study the routing constraints of Virtex devices and we propose a systematic methodology for designing a novel general-purpose interconnection network targeting to reconfigurable architectures. This network consists of multiple segment wires and SB patterns, appropriately selected and assigned across the device. The goal of our proposed methodology is to maximize the hardware utilization of fabricated routing resources. The derived interconnection scheme is integrated on a Virtex style FPGA. This device is characterized both for its high-performance, as well as for its low-energy requirements. Due to this, the design criterion that guides our architecture selections was the minimal Energy×Delay Product (EDP). The methodology is fully-supported by three new software tools, which belong to MEANDER Design Framework. Using a typical set of MCNC benchmarks, extensive comparison study in terms of several critical parameters proves the effectiveness of the derived interconnection network. More specifically, we achieve average Energy×Delay Product reduction by 63%, performance increase by 26%, reduction in leakage power by 21%, reduction in total energy consumption by 11%, at the expense of increase of channel width by 20%.
Abstract: This paper mathematically analyses the varying
magnitude of production loss, which may occur due to idle time (inprocess
waiting time and traveling time) on a linear walking worker
assembly line. Within this flexible and reconfigurable assembly
system, each worker travels down the line carrying out each
assembly task at each station; and each worker accomplishes the
assembly of a unit from start to finish and then travels back to the
first station to start the assembly of a new product. This strategy of
system design attempts to combine the flexibility of the U-shaped
moving worker assembly cell with the efficiency of the conventional
fixed worker assembly line. The paper aims to evaluate the effect of
idle time that may offset the labor efficiency of each walking worker
providing an insight into the mechanism of such a flexible and
reconfigurable assembly system.
Abstract: A multi-board run-time reconfigurable (MRTR)
system for evolvable hardware (EHW) is introduced with the aim to
implement on hardware the bidirectional incremental evolution (BIE)
method. The main features of this digital intrinsic EHW solution rely
on the multi-board approach, the variable chromosome length
management and the partial configuration of the reconfigurable
circuit. These three features provide a high scalability to the solution.
The design has been written in VHDL with the concern of not being
platform dependant in order to keep a flexibility factor as high as
possible. This solution helps tackling the problem of evolving
complex task on digital configurable support.
Abstract: We demonstrate a 1×4 coarse wavelength
division-multiplexing (CWDM) planar concave grating
multiplexer/demultiplexer and its application in re-configurable
optical add/drop multiplexer (ROADM) system in silicon-on-insulator
substrate. The wavelengths of the demonstrated concave grating
multiplexer align well with the ITU-T standard. We demonstrate a
prototype of ROADM comprising two such concave gratings and four
wide-band thermo-optical MZI switches. Undercut technology which
removes the underneath silicon substrate is adopted in optical switches
in order to minimize the operation power. For all the thermal heaters,
the operation voltage is smaller than 1.5 V, and the switch power is
~2.4 mW. High throughput pseudorandom binary sequence (PRBS)
data transmission with up to 100 Gb/s is demonstrated, showing the
high-performance ROADM functionality.
Abstract: This paper proposes a low-cost reconfigurable
architecture for AES algorithm. The proposed architecture separates
SubBytes and MixColumns into two parallel data path, and supports
different bit-width operation for this two data path. As a result, different number of S-box can be supported in this architecture. The
throughput and power consumption can be adjusted by changing the
number of S-box running in this design. Using the TSMC 0.18μm CMOS standard cell library, a very low-cost implementation of 7K
Gates is obtained under 182MHz frequency. The maximum throughput is 360Mbps while using 4 S-Box simultaneously, and the
minimum throughput is 114Mbps while only using 1 S-Box
Abstract: As business environments are rapidly changing,
the manufacturing system must be reconfigured to adapt to
various customer needs. In order to cope with this challenge, it
is quintessential to test industrial control logic rapidly and
easily in the design time, and monitor operational behavior in
the run time of automated manufacturing system. Proposed
integrated model for virtual prototyping and operational
monitoring of industrial control logic is to improve limitations
of current ladder programming practices and general discrete
event simulation method. Each plant layout model using HMI
package and object-oriented control logic model is designed
independently and is executed simultaneously in integrated
manner to reflect design practices of automation system in the
design time. Control logic is designed and executed using UML
activity diagram without considering complicated control
behavior to deal with current trend of reconfigurable
manufacturing. After the physical installation, layout model of
virtual prototype constructed in the design time is reused for
operational monitoring of system behavior during run time.