Pulsed Multi-Layered Image Filtering: A VLSI Implementation

Image convolution similar to the receptive fields found in mammalian visual pathways has long been used in conventional image processing in the form of Gabor masks. However, no VLSI implementation of parallel, multi-layered pulsed processing has been brought forward which would emulate this property. We present a technical realization of such a pulsed image processing scheme. The discussed IC also serves as a general testbed for VLSI-based pulsed information processing, which is of interest especially with regard to the robustness of representing an analog signal in the phase or duration of a pulsed, quasi-digital signal, as well as the possibility of direct digital manipulation of such an analog signal. The network connectivity and processing properties are reconfigurable so as to allow adaptation to various processing tasks.

Authors:

• Christian Mayr
• Holger Eisenreich
• Stephan Henker
• René Schüffny

Keywords:

• Neural image processing
• pulse computation application
• pulsed Gabor convolution
• VLSI pulse routing.

References:

[1] J. Schreiter, U. Ramacher, A. Heittmann, D. Matolin, and R. Sch├╝ffny,
"Cellular pulse coupled neural network with adaptive weights for image
segmentation and its VLSI implementation," in Proc. IS&T/SPIE 16th
International Symposium on Electronic Imaging: Science and
Technology, San Jose (CA), USA, 2004, 5298, pp. 290-296.
[2] Y. Ota and B.M. Wilamowski, "CMOS architecture of synchronous
pulse-coupled neural network and its application to image processing,"
in Proc. of the 26th Annual Conference of the IEEE Industrial
Electronics Society (IECON'00), Nagoya, Japan, 2000, pp. 1213-1218.
[3] Bernd Richter, "Development of a readout circuit for pulse-coupled
artificial neural networks," Diploma thesis, University of Technology
Dresden, Endowed Chair for Neural Circuits and Parallel VLSI-Systems,
Dresden, Germany, 2003.
[4] D.H. Hubel and T.N. Wiesel, "Receptive fields and functional
architecture of monkey striate cortex," Journal of Physiology, vol. 195,
no. 1, pp. 215-243, March 1968.
[5] C. Koch, Biophysics of computation - information processing in single
neurons, Oxford University Press, Oxford, 1999.
[6] W. Maass, T. Natschläger, and H. Markram, "Real-time computing
without stable states: a new framework for neural computation based on
perturbations," Neural Computation, vol. 14, no. 11, pp. 2531-2560,
Nov. 2002.
[7] A. Heittmann and U. Ramacher, "An architecture for feature detection
utilizing dynamic synapses," in Proc. of the 47th IEEE International
Midwest Symposium on Circuits and Systems, Hiroshima, Japan, 2004,
pp. II-373 - II-376.
[8] P. Benkart, A. Heitmann, H. Huebner, U. Ramacher,, A. Kaiser, A.
Munding, M. Bschorr, H.-J. Pfleiderer, E. Kohn, "3D chip stack
technology using through-chip interconnects," IEEE Journal of Design
& Test of Computers, vol. 22, no. 6, pp. 512-518, Nov. 2005.
[9] A. Munding, Department of Electron Devices and Circuits, University of
Ulm, Ulm, Germany, private communication, July 2005.