Abstract: The IEEE 802.15.4 standard is designed for low-rate wireless personal area networks (LR-WPAN) with focus on enabling wireless sensor networks. It aims to give a low data rate, low power consumption, and low cost wireless networking on the device-level communication. The objective of this study is to investigate the performance of IEEE 802.15.4 based networks using simulation tool. In this project the network simulator 2 NS2 was used to several performance measures of wireless sensor networks. Three scenarios were considered, multi hop network with a single coordinator, star topology, and an ad hoc on demand distance vector AODV. Results such as packet delivery ratio, hop delay, and number of collisions are obtained from these scenarios.
Abstract: This paper deals with a mini radar system aimed at detecting small targets at the low latitude. The radar operates at Ku-band in the frequency modulated continuous wave (FMCW) mode with two receiving channels. The radar system has the characteristics of compactness, mobility, and low power consumption. This paper focuses on the implementation of the radar system, and the Block least mean square (Block LMS) algorithm is applied to minimize the fortuitous distortion. It is validated from a series of experiments that the track of the unmanned aerial vehicle (UAV) can be easily distinguished with the radar system.
Abstract: Pilot stages are one of the most common positioners and regulators in industry. In this paper, we present two novel concepts for pilot stages with low power consumption to regulate a pneumatic device. Pilot 1, first concept, is designed based on a conventional frame core electro-magnetic actuator and a leaf spring to control the air flow and pilot 2 has an axisymmetric actuator and spring made of non-oriented electrical steel. Concepts are simulated in a system modeling tool to study their dynamic behavior. Both concepts are prototyped and tested. Experimental results are comprehensively analyzed and compared. The most promising concept that consumes less than 8 mW is highlighted and presented.
Abstract: Nowadays, the European Ecodesign Directive has emerged as a new approach to integrate environmental concerns into the product design and related processes. Ecodesign aims to minimize environmental impacts throughout the product life cycle, without compromising performances and costs. In addition, the recent Ecodesign Directives require products which are increasingly eco-friendly and eco-efficient, preserving high-performances. It is very important for producers measuring performances, for electric cooking ranges, hobs, ovens, and grills for household use, and a low power consumption of appliances represents a powerful selling point, also in terms of ecodesign requirements. The Ecodesign Directive provides a clear framework about the sustainable design of products and it has been extended in 2009 to all energy-related products, or products with an impact on energy consumption during the use. The European Regulation establishes measures of ecodesign of ovens, hobs, and kitchen hoods, and domestic use and energy efficiency of a product has a significant environmental aspect in the use phase which is the most impactful in the life cycle. It is important that the product parameters and performances are not affected by ecodesign requirements from a user’s point of view, and the benefits of reducing energy consumption in the use phase should offset the possible environmental impact in the production stage. Accurate measurements of cooking appliance performance are essential to help the industry to produce more energy efficient appliances. The development of ecodriven products requires ecoinnovation and ecodesign tools to support the sustainability improvement. The ecodesign tools should be practical and focused on specific ecoobjectives in order to be largely diffused. The main scope of this paper is the development, implementation, and testing of an innovative tool, which could be an improvement for the sustainable design of induction hobs. In particular, a prototypical software tool is developed in order to simulate the energy performances of the induction hobs. The tool is focused on a multiphysics model which is able to simulate the energy performances and the efficiency of induction hobs starting from the design data. The multiphysics model is composed by an electromagnetic simulation and a thermal simulation. The electromagnetic simulation is able to calculate the eddy current induced in the pot, which leads to the Joule heating of material. The thermal simulation is able to measure the energy consumption during the operational phase. The Joule heating caused from the eddy currents is the output of electromagnetic simulation and the input of thermal ones. The aims of the paper are the development of integrated tools and methodologies of virtual prototyping in the context of the ecodesign. This tool could be a revolutionary instrument in the field of industrial engineering and it gives consideration to the environmental aspects of product design and focus on the ecodesign of energy-related products, in order to achieve a reduced environmental impact.
Abstract: Recursive combination of an algorithm based on Karatsuba multiplication is exploited to design a generalized transpose and parallel Finite Impulse Response (FIR) Filter. Mid-range Karatsuba multiplication and Carry Save adder based on Karatsuba multiplication reduce time complexity for higher order multiplication implemented up to n-bit. As a result, we design modified N-tap Transpose and Parallel Symmetric FIR Filter Structure using Karatsuba algorithm. The mathematical formulation of the FFA Filter is derived. The proposed architecture involves significantly less area delay product (APD) then the existing block implementation. By adopting retiming technique, hardware cost is reduced further. The filter architecture is designed by using 90 nm technology library and is implemented by using cadence EDA Tool. The synthesized result shows better performance for different word length and block size. The design achieves switching activity reduction and low power consumption by applying with and without retiming for different combination of the circuit. The proposed structure achieves more than a half of the power reduction by adopting with and without retiming techniques compared to the earlier design structure. As a proof of the concept for block size 16 and filter length 64 for CKA method, it achieves a 51% as well as 70% less power by applying retiming technique, and for CSA method it achieves a 57% as well as 77% less power by applying retiming technique compared to the previously proposed design.
Abstract: In this paper, a low voltage high performance current mirror is presented. Its most important specifications, which are improved in this work, are analyzed and formulated proving that it has such outstanding merits as: Very low input resistance of 26mΩ, very wide current dynamic range of 8 decades from 10pA to 1mA (160dB) together with an extremely low current copy error of less than 0.6ppm, and very low input and output voltages. Furthermore, the proposed current mirror bandwidth is 944MHz utilizing very low power consumption (267μW) and transistors count. HSPICE simulation results are performed using TSMC 0.18μm CMOS technology utilizing 1.8V single power supply, confirming the theoretically proved outstanding performance of the proposed current mirror. Monte Carlo simulation of its most important parameter is also examined showing its sufficiently resistance against technology process variations.
Abstract: The main issue in designing a wireless sensor network
(WSN) is the finding of a proper routing protocol that complies with
the several requirements of high reliability, short latency, scalability,
low power consumption, and many others. This paper proposes a
novel routing algorithm that complies with these design
requirements. The new routing protocol divides the WSN into several subnetworks
and each sub-network is divided into several clusters. This
division is designed to reduce the number of radio transmission and
hence decreases the power consumption. The network division may
be changed dynamically to adapt with the network changes and
allows the realization of the design requirements.
Abstract: In this study, we developed a complementary electrochromic device consisting of WO3 and NiO films fabricated by rf-magnetron sputtered. The electrochromic properties of WO3 and NiO films were investigated using cyclic voltammograms (CV), performed on WO3 and NiO films immersed in an electrolyte of 1 M LiClO4 in propylene carbonate (PC). Optical and electrochemical of the films, as a function of coloration–bleaching cycle, were characterized using an UV-Vis-NIR spectrophotometer and cyclic voltammetry (CV). After investigating the properties of WO3 film, NiO film, and complementary electrochromic devices, we concluded that this device provides good reversibility, low power consumption of -2.5 V in color state, high variation of transmittance of 58.96%, changes in optical density of 0.81 and good memory effect under open-circuit conditions. In addition, electrochromic component penetration rate can be retained below 20% within 24h, showing preferred memory features; however, component coloring and bleaching response time are about 33s.
Abstract: Digital systems are said to be constructed using basic logic gates. These gates are the NOR, NAND, AND, OR, EXOR & EXNOR gates. This paper presents a robust three transistors (3T) based NAND and NOR gates with precise output logic levels, yet maintaining equivalent performance than the existing logic structures. This new set of 3T logic gates are based on CMOS inverter and Pass Transistor Logic (PTL). The new universal logic gates are characterized by better speed and lower power dissipation which can be straightforwardly fabricated as memory ICs for high performance computer networks. The simulation tests were performed using standard BPTM 22nm process technology using SYNOPSYS HSPICE. The 3T NAND gate is evaluated using C17 benchmark circuit and 3T NOR is gate evaluated using a D-Latch. According to HSPICE simulation in 22 nm CMOS BPTM process technology under given conditions and at room temperature, the proposed 3T gates shows an improvement of 88% less power consumption on an average over conventional CMOS logic gates. The devices designed with 3T gates will make longer battery life by ensuring extremely low power consumption.
Abstract: This paper aims to present the design, fabrication and test of a novel piezoelectric actuated, check-valves embedded micropump having the advantages of miniature size, light weight and low power consumption. This device is designed to pump gases and liquids with the capability of performing the self-priming and bubble-tolerant work mode by maximizing the stroke volume of the membrane as well as the compression ratio via minimization of the dead volume of the micropump chamber and channel. By experiment apparatus setup, we can get the real-time values of the flow rate of micropump, the displacement of the piezoelectric actuator and the deformation of the check valve, simultaneously. The micropump with check valve 0.4 mm in thickness obtained higher output performance under the sinusoidal waveform of 120 Vpp. The micropump achieved the maximum pumping rates of 42.2 ml/min and back pressure of 14.0 kPa at the corresponding frequency of 28 and 20 Hz. The presented micropump is able to pump gases with a pumping rate of 196 ml/min at operating frequencies of 280 Hz under the sinusoidal waveform of 120 Vpp.
Abstract: Low power consumption is a major constraint for battery-powered system like computer notebook or PDA. In the past, specialists usually designed both specific optimized equipments and codes to relief this concern. Doing like this could work for quite a long time, however, in this era, there is another significant restraint, the time to market. To be able to serve along the power constraint while can launch products in shorter production period, objectoriented programming (OOP) has stepped in to this field. Though everyone knows that OOP has quite much more overhead than assembly and procedural languages, development trend still heads to this new world, which contradicts with the target of low power consumption. Most of the prior power related software researches reported that OOP consumed much resource, however, as industry had to accept it due to business reasons, up to now, no papers yet had mentioned about how to choose the best OOP practice in this power limited boundary. This article is the pioneer that tries to specify and propose the optimized strategy in writing OOP software under energy concerned environment, based on quantitative real results. The language chosen for studying is C# based on .NET Framework 2.0 which is one of the trendy OOP development environments. The recommendation gotten from this research would be a good roadmap that can help developers in coding that well balances between time to market and time of battery.
Abstract: The use of Quantum dots is a promising emerging
Technology for implementing digital system at the nano level. It is
effecient for attractive features such as faster speed , smaller size and
low power consumption than transistor technology. In this paper,
various Combinational and sequential logical structures - HALF
ADDER, SR Latch and Flip-Flop, D Flip-Flop preceding NAND,
NOR, XOR,XNOR are discussed based on QCA design, with
comparatively less number of cells and area. By applying these
layouts, the hardware requirements for a QCA design can be reduced.
These structures are designed and simulated using QCA Designer
Tool. By taking full advantage of the unique features of this
technology, we are able to create complete circuits on a single layer
of QCA. Such Devices are expected to function with ultra low
power Consumption and very high speeds.
Abstract: Design Patterns have gained more and more
acceptances since their emerging in software development world last
decade and become another de facto standard of essential knowledge
for Object-Oriented Programming developers nowadays.
Their target usage, from the beginning, was for regular computers,
so, minimizing power consumption had never been a concern.
However, in this decade, demands of more complicated software for
running on mobile devices has grown rapidly as the much higher
performance portable gadgets have been supplied to the market
continuously. To get along with time to market that is business
reason, the section of software development for power conscious,
battery, devices has shifted itself from using specific low-level
languages to higher level ones. Currently, complicated software
running on mobile devices are often developed by high level
languages those support OOP concepts. These cause the trend of
embracing Design Patterns to mobile world.
However, using Design Patterns directly in software development
for power conscious systems is not recommended because they were
not originally designed for such environment. This paper
demonstrates the adapted Design Pattern for power limitation system.
Because there are numerous original design patterns, it is not possible
to mention the whole at once. So, this paper focuses only in creating
Energy Conscious version of existing regular "Builder Pattern" to be
appropriated for developing low power consumption software.
Abstract: This paper presents two prototypes of low power low voltage current mode 9 bit pipelined a/d converters. The first and the second converters are configured of 1.5 bit and 2.5 bit stages, respectively. The a/d converter structures are composed of current mode building blocks and final comparator block which converts the analog current signal into digital voltage signal. All building blocks have been designed in CMOS AMS 0.35μm technology, then simulated to verify proposed concept. The performances of both converters are compared to performances of known current mode and voltage mode switched capacitance converter structures. Low power consumption and small chip area are advantages of the proposed converters.
Abstract: Although White LED lighting systems powered by solar cells have presented for many years, they are not widely used in today application because of their cost and low energy conversion efficiency. The proposed system use the dc power generated by fixed solar cells module to energize White LED light sources that are operated by directly connected White LED with current limitation resistors, resulting in much more power consumption. This paper presents the use of white LED as a general lighting application powered by tracking solar cells module and using pulse to apply the electrical power to the White LED. These systems resulted in high efficiency power conversion, low power consumption, and long light of the white LED.
Abstract: This paper presents the design of a low power second-order continuous-time sigma-delta modulator for low power
applications. The loop filter of this modulator has been implemented based on the nonlinear transconductance-capacitor (Gm-C) by employing current-mode technique. The nonlinear transconductance uses floating gate MOS (FG-MOS) transistors that operate in weak inversion region. The proposed modulator features low power consumption (
Abstract: In this paper, based on a novel synthesis, a set of new simplified circuit design to implement the linguistic-hedge operations for adjusting the fuzzy membership function set is presented. The circuits work in current-mode and employ floating-gate MOS (FGMOS) transistors that operate in weak inversion region. Compared to the other proposed circuits, these circuits feature severe reduction of the elements number, low supply voltage (0.7V), low power consumption (60dB). In this paper, a set of fuzzy linguistic hedge circuits, including absolutely, very, much more, more, plus minus, more or less and slightly, has been implemented in 0.18 mm CMOS process. Simulation results by Hspice confirm the validity of the proposed design technique and show high performance of the circuits.
Abstract: In this paper we present a novel design of a wearable
electronic textile. After defining a special application, we used the
specifications of some low power, tiny elements including sensors,
microcontrollers, transceivers, and a fault tolerant special topology to
have the most reliability as well as low power consumption and
longer lifetime. We have considered two different conditions as
normal and bodily critical conditions and set priorities for using
different sensors in various conditions to have a longer effective
lifetime.
Abstract: In this present work, the development of an avionics
system for flight data collection of a Raptor 30 V2 is carried out. For the data acquisition both onground and onboard avionics systems are developed for testing of a small-scale Unmanned Aerial Vehicle
(UAV) helicopter. The onboard avionics record the helicopter state
outputs namely accelerations, angular rates and Euler angles, in real time, and the on ground avionics system record the inputs given to
the radio controlled helicopter through a transmitter, in real time. The avionic systems are designed and developed taking into consideration
low weight, small size, anti-vibration, low power consumption, and easy interfacing. To mitigate the medium frequency vibrations
embedded on the UAV helicopter during flight, a damper is designed
and its performance is evaluated. A number of flight tests are carried
out and the data obtained is then analyzed for accuracy and repeatability and conclusions are inferred.
Abstract: A new low-voltage floating gate MOSFET (FGMOS)
based squarer using square law characteristic of the FGMOS is
proposed in this paper. The major advantages of the squarer are simplicity,
rail-to-rail input dynamic range, low total harmonic distortion,
and low power consumption. The proposed circuit is biased without
body effect. The circuit is designed and simulated using SPICE in
0.25μm CMOS technology. The squarer is operated at the supply
voltages of ±0.75V . The total harmonic distortion (THD) for the
input signal 0.75Vpp at 25 KHz, and maximum power consumption
were found to be less than 1% and 319μW respectively.