Abstract: Midpoint filter is quite effective in recovering the
images confounded by the short-tailed (uniform) noise. It, however,
performs poorly in the presence of additive long-tailed (impulse)
noise and it does not preserve the edge structures of the image
signals. Median smoother discards outliers (impulses) effectively, but
it fails to provide adequate smoothing for images corrupted with nonimpulse
noise. In this paper, two nonlinear techniques for image
filtering, namely, New Filter I and New Filter II are proposed based
on a nonlinear high-pass filter algorithm. New Filter I is constructed
using a midpoint filter, a highpass filter and a combiner. It suppresses
uniform noise quite well. New Filter II is configured using an alpha
trimmed midpoint filter, a median smoother of window size 3x3, the
high pass filter and the combiner. It is robust against impulse noise
and attenuates uniform noise satisfactorily. Both the filters are shown
to exhibit good response at the image boundaries (edges). The
proposed filters are evaluated for their performance on a test image
and the results obtained are included.
Abstract: .Hardware realization of a Neural Network (NN), to a large extent depends on the efficient implementation of a single neuron. FPGA-based reconfigurable computing architectures are suitable for hardware implementation of neural networks. FPGA realization of ANNs with a large number of neurons is still a challenging task. This paper discusses the issues involved in implementation of a multi-input neuron with linear/nonlinear excitation functions using FPGA. Implementation method with resource/speed tradeoff is proposed to handle signed decimal numbers. The VHDL coding developed is tested using Xilinx XC V50hq240 Chip. To improve the speed of operation a lookup table method is used. The problems involved in using a lookup table (LUT) for a nonlinear function is discussed. The percentage saving in resource and the improvement in speed with an LUT for a neuron is reported. An attempt is also made to derive a generalized formula for a multi-input neuron that facilitates to estimate approximately the total resource requirement and speed achievable for a given multilayer neural network. This facilitates the designer to choose the FPGA capacity for a given application. Using the proposed method of implementation a neural network based application, namely, a Space vector modulator for a vector-controlled drive is presented
Abstract: Median filters with larger windows offer greater smoothing and are more robust than the median filters of smaller windows. However, the larger median smoothers (the median filters with the larger windows) fail to track low order polynomial trends in the signals. Due to this, constant regions are produced at the signal corners, leading to the loss of fine details. In this paper, an algorithm, which combines the ability of the 3-point median smoother in preserving the low order polynomial trends and the superior noise filtering characteristics of the larger median smoother, is introduced. The proposed algorithm (called the combiner algorithm in this paper) is evaluated for its performance on a test image corrupted with different types of noise and the results obtained are included.