Abstract: This paper reports on the impact study with the variation of the gate insulation material and thickness on different models of pocket implanted sub-100 nm n-MOS device. The gate materials used here are silicon dioxide (SiO2), aluminum silicate (Al2SiO5), silicon nitride (Si3N4), alumina (Al2O3), hafnium silicate (HfSiO4), tantalum pentoxide (Ta2O5), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), and lanthanum oxide (La2O3) upon a p-type silicon substrate material. The gate insulation thickness was varied from 2.0 nm to 3.5 nm for a 50 nm channel length pocket implanted n-MOSFET. There are several models available for this device. We have studied and simulated threshold voltage model incorporating drain and substrate bias effects, surface potential, inversion layer charge, pinch-off voltage, effective electric field, inversion layer mobility, and subthreshold drain current models based on two linear symmetric pocket doping profiles. We have changed the values of the two parameters, viz. gate insulation material and thickness gradually fixing the other parameter at their typical values. Then we compared and analyzed the simulation results. This study would be helpful for the nano-scaled MOS device designers for various applications to predict the device behavior.
Abstract: In this paper, we present and investigate a double gate PN diode based tunnel field effect transistor (DGPNTFET). The importance of proposed structure is that the formation of different drain doping is not required and ambipolar effect in OFF state is completely removed for this structure. Validation of this structure to behave like a Tunnel Field Effect Transistor (TFET) is carried out through energy band diagrams and transfer characteristics. Simulated result shows point subthreshold slope (SS) of 19.14 mV/decade and ON to OFF current ratio (ION / IOFF) of 2.66 × 1014 (ION at VGS=1.5V, VDS=1V and IOFF at VGS=0V, VDS=1V) for gate length of 20nm and HfO2 as gate oxide at room temperature. Which indicate that the DGPNTFET is a promising candidate for nano-scale, ambipolar free switch.
Abstract: The paper presents a simulation study of the electrical
characteristic of Bulk Planar Junctionless Transistor (BPJLT) using
spacer. The BPJLT is a transistor without any PN junctions in the
vertical direction. It is a gate controlled variable resistor. The
characteristics of BPJLT are analyzed by varying the oxide material
under the gate. It can be shown from the simulation that an ideal
subthreshold slope of ~60 mV/decade can be achieved by using highk
dielectric. The effects of variation of spacer length and material on
the electrical characteristic of BPJLT are also investigated in the
paper. The ION / IOFF ratio improvement is of the order of 107 and the
OFF current reduction of 10-4 is obtained by using gate dielectric of
HfO2 instead of SiO2.
Abstract: In this paper, the transient device performance analysis
of n-type Gate Inside JunctionLess Transistor (GI-JLT) has been
evaluated. 3-D Bohm Quantum Potential (BQP) transport device
simulation has been used to evaluate the delay and power dissipation
performance. GI-JLT has a number of desirable device parameters
such as reduced propagation delay, dynamic power dissipation,
power and delay product, intrinsic gate delay and energy delay
product as compared to Gate-all-around transistors GAA-JLT. In
addition to this, various other device performance parameters namely,
on/off current ratio, short channel effects (SCE), transconductance
Generation Factor (TGF) and unity gain cut-off frequency (fT ) and
subthreshold slope (SS) of the GI-JLT and GAA-JLT have been
analyzed and compared. GI-JLT shows better device performance
characteristics than GAA-JLT for low power and high frequency
applications, because of its larger gate electrostatic control on the
device operation.
Abstract: Carrier scatterings in the inversion channel of MOSFET dominates the carrier mobility and hence drain current. This paper presents an analytical model of the subthreshold drain current incorporating the effective electron mobility model of the pocket implanted nano scale n-MOSFET. The model is developed by assuming two linear pocket profiles at the source and drain edges at the surface and by using the conventional drift-diffusion equation. Effective electron mobility model includes three scattering mechanisms, such as, Coulomb, phonon and surface roughness scatterings as well as ballistic phenomena in the pocket implanted n-MOSFET. The model is simulated for various pocket profile and device parameters as well as for various bias conditions. Simulation results show that the subthreshold drain current data matches the experimental data already published in the literature.
Abstract: We discuss the signal detection through nonlinear
threshold systems. The detection performance is assessed by the
probability of error Per . We establish that: (1) when the signal is
complete suprathreshold, noise always degrades the signal detection
both in the single threshold system and in the parallel array of
threshold devices. (2) When the signal is a little subthreshold, noise
degrades signal detection in the single threshold system. But in the
parallel array, noise can improve signal detection, i.e., stochastic
resonance (SR) exists in the array. (3) When the signal is predominant
subthreshold, noise always can improve signal detection and SR
always exists not only in the single threshold system but also in the
parallel array. (4) Array can improve signal detection by raising the
number of threshold devices. These results extend further the
applicability of SR in signal detection.
Abstract: In this paper, we have proposed a novel FinFET with
extended body under the poly gate, which is called EB-FinFET, and
its characteristic is demonstrated by using three-dimensional (3-D)
numerical simulation. We have analyzed and compared it with
conventional FinFET. The extended body height dependence on the
drain induced barrier lowering (DIBL) and subthreshold swing (S.S)
have been also investigated. According to the 3-D numerical
simulation, the proposed structure has a firm structure, an acceptable
short channel effect (SCE), a reduced series resistance, an increased
on state drain current (I
on) and a large normalized I
DS. Furthermore,
the structure can also improve corner effect and reduce self-heating
effect due to the extended body. Our results show that the EBFinFET
is excellent for nanoscale device.
Abstract: We fabricated the inverted-staggered etch stopper
structure oxide-based TFT and investigated the characteristics of oxide
TFT under the 400 nm wavelength light illumination. When 400 nm
light was illuminated, the threshold voltage (Vth) decreased and
subthreshold slope (SS) increased at forward sweep, while Vth and SS
were not altered when larger wavelength lights, such as 650 nm, 550
nm and 450 nm, were illuminated. At reverse sweep, the transfer curve
barely changed even under 400 nm light. Our experimental results
support that photo-induced hole carriers are captured by donor-like
interface trap and it caused the decrease of Vth and increase of SS. We
investigated the interface trap density increases proportionally to the
photo-induced hole concentration at active layer.
Abstract: In this paper, we propose a novel metal oxide
semiconductor field effect transistor with L-shaped channel structure
(LMOS), and several type of L-shaped structures are also designed,
studied and compared with the conventional MOSFET device for the
same average gate length (Lavg). The proposed device electrical
characteristics are analyzed and evaluated by three dimension (3-D)
ISE-TCAD simulator. It can be confirmed that the LMOS devices
have higher on-state drain current and both lower drain-induced
barrier lowering (DIBL) and subthreshold swing (S.S.) than its
conventional counterpart has. In addition, the transconductance and
voltage gain properties of the LMOS are also improved.
Abstract: Stochastic resonance (SR) is a phenomenon whereby
the signal transmission or signal processing through certain nonlinear
systems can be improved by adding noise. This paper discusses SR in
nonlinear signal detection by a simple test statistic, which can be
computed from multiple noisy data in a binary decision problem based
on a maximum a posteriori probability criterion. The performance of
detection is assessed by the probability of detection error Per . When
the input signal is subthreshold signal, we establish that benefit from
noise can be gained for different noises and confirm further that the
subthreshold SR exists in nonlinear signal detection. The efficacy of
SR is significantly improved and the minimum of Per can
dramatically approach to zero as the sample number increases. These
results show the robustness of SR in signal detection and extend the
applicability of SR in signal processing.
Abstract: Ultra-low-power (ULP) circuits have received
widespread attention due to the rapid growth of biomedical
applications and Battery-less Electronics. Subthreshold region of
transistor operation is used in ULP circuits. Major research challenge
in the subthreshold operating region is to extract the ULP benefits
with minimal degradation in speed and robustness. Process, Voltage
and Temperature (PVT) variations significantly affect the
performance of subthreshold circuits. Designed performance
parameters of ULP circuits may vary largely due to temperature
variations. Hence, this paper investigates the effect of temperature
variation on device and circuit performance parameters at different
biasing voltages in the subthreshold region. Simulation results clearly
demonstrate that in deep subthreshold and near threshold voltage
regions, performance parameters are significantly affected whereas in
moderate subthreshold region, subthreshold circuits are more
immune to temperature variations. This establishes that moderate
subthreshold region is ideal for temperature immune circuits.
Abstract: In this paper, gate leakage current has been mitigated
by the use of novel nanoscale MOSFET with Source/Drain-to-Gate
Non-overlapped and high-k spacer structure for the first time. A
compact analytical model has been developed to study the gate
leakage behaviour of proposed MOSFET structure. The result
obtained has found good agreement with the Sentaurus Simulation.
Fringing gate electric field through the dielectric spacer induces
inversion layer in the non-overlap region to act as extended S/D
region. It is found that optimal Source/Drain-to-Gate Non-overlapped
and high-k spacer structure has reduced the gate leakage current to
great extent as compared to those of an overlapped structure. Further,
the proposed structure had improved off current, subthreshold slope
and DIBL characteristic. It is concluded that this structure solves the
problem of high leakage current without introducing the extra series
resistance.
Abstract: In this paper electrical characteristics of various kinds
of multiple-gate silicon nanowire transistors (SNWT) with the
channel length equal to 7 nm are compared. A fully ballistic quantum
mechanical transport approach based on NEGF was employed to
analyses electrical characteristics of rectangular and cylindrical
silicon nanowire transistors as well as a Double gate MOS FET. A
double gate, triple gate, and gate all around nano wires were studied
to investigate the impact of increasing the number of gates on the
control of the short channel effect which is important in nanoscale
devices. Also in the case of triple gate rectangular SNWT inserting
extra gates on the bottom of device can improve the application of
device. The results indicate that by using gate all around structures
short channel effects such as DIBL, subthreshold swing and delay
reduces.