Abstract: Data driven dynamic logic is the high speed dynamic circuit with low area. The clock of the dynamic circuit is removed and data drives the circuit instead of clock for precharging purpose. This data driven dynamic nand gate is given static forward substrate biasing of Vsupply/2 as well as the substrate bias is connected to the input data, resulting in dynamic substrate bias. The dynamic substrate bias gives the shortest propagation delay with a penalty on the power dissipation. Propagation delay is reduced by 77.8% compared to the normal reverse substrate bias Data driven dynamic nand. Also dynamic substrate biased D3nand’s propagation delay is reduced by 31.26% compared to data driven dynamic nand gate with static forward substrate biasing of Vdd/2. This data driven dynamic nand gate with dynamic body biasing gives us the highest speed with no area penalty and finds its applications where power penalty is acceptable. Also combination of Dynamic and static Forward body bias can be used with reduced propagation delay compared to static forward biased circuit and with comparable increase in an average power. The simulations were done on hspice simulator with 22nm High-k metal gate strained Si technology HP models of Arizona State University, USA.
Abstract: The paper presents a simulation study of the electrical
characteristic of Bulk Planar Junctionless Transistor (BPJLT) using
spacer. The BPJLT is a transistor without any PN junctions in the
vertical direction. It is a gate controlled variable resistor. The
characteristics of BPJLT are analyzed by varying the oxide material
under the gate. It can be shown from the simulation that an ideal
subthreshold slope of ~60 mV/decade can be achieved by using highk
dielectric. The effects of variation of spacer length and material on
the electrical characteristic of BPJLT are also investigated in the
paper. The ION / IOFF ratio improvement is of the order of 107 and the
OFF current reduction of 10-4 is obtained by using gate dielectric of
HfO2 instead of SiO2.
Abstract: This paper presents a new compact analytical model of
the gate leakage current in high-k based nano scale MOSFET by
assuming a two-step inelastic trap-assisted tunneling (ITAT) process
as the conduction mechanism. This model is based on an inelastic
trap-assisted tunneling (ITAT) mechanism combined with a semiempirical
gate leakage current formulation in the BSIM 4 model. The
gate tunneling currents have been calculated as a function of gate
voltage for different gate dielectrics structures such as HfO2, Al2O3
and Si3N4 with EOT (equivalent oxide thickness) of 1.0 nm. The
proposed model is compared and contrasted with santaurus
simulation results to verify the accuracy of the model and excellent
agreement is found between the analytical and simulated data. It is
observed that proposed analytical model is suitable for different highk
gate dielectrics simply by adjusting two fitting parameters. It was
also shown that gate leakages reduced with the introduction of high-k
gate dielectric in place of SiO2.
Abstract: In this paper, gate leakage current has been mitigated
by the use of novel nanoscale MOSFET with Source/Drain-to-Gate
Non-overlapped and high-k spacer structure for the first time. A
compact analytical model has been developed to study the gate
leakage behaviour of proposed MOSFET structure. The result
obtained has found good agreement with the Sentaurus Simulation.
Fringing gate electric field through the dielectric spacer induces
inversion layer in the non-overlap region to act as extended S/D
region. It is found that optimal Source/Drain-to-Gate Non-overlapped
and high-k spacer structure has reduced the gate leakage current to
great extent as compared to those of an overlapped structure. Further,
the proposed structure had improved off current, subthreshold slope
and DIBL characteristic. It is concluded that this structure solves the
problem of high leakage current without introducing the extra series
resistance.
Abstract: In this paper, we have developed an explicit analytical
drain current model comprising surface channel potential and
threshold voltage in order to explain the advantages of the proposed
Gate Stack Double Diffusion (GSDD) MOSFET design over the
conventional MOSFET with the same geometric specifications that
allow us to use the benefits of the incorporation of the high-k layer
between the oxide layer and gate metal aspect on the immunity of the
proposed design against the self-heating effects. In order to show the
efficiency of our proposed structure, we propose the simulation of the
power chopper circuit. The use of the proposed structure to design a
power chopper circuit has showed that the (GSDD) MOSFET can
improve the working of the circuit in terms of power dissipation and
self-heating effect immunity. The results so obtained are in close
proximity with the 2D simulated results thus confirming the validity
of the proposed model.