Abstract: Digital magnitude comparators based on Gate Diffusion Input (GDI) implementation technique are high speed and area-efficient, and they consume less power as compared to other implementation techniques. However, they are less efficient for some logic gates and have no full voltage swing. In this paper, we made a performance comparison between the GDI implementation technique and other implementation methods, such as Static CMOS, Pass Transistor Logic (PTL), and Transmission Gate (TG) in 90 nm, 120 nm, and 180 nm CMOS technologies using BSIM4 MOS model. We proposed a methodology (hybrid implementation) of implementing digital magnitude comparators which significantly improved the power, speed, area, and voltage swing requirements. Simulation results revealed that the hybrid implementation of digital magnitude comparators show a 10.84% (power dissipation), 41.6% (propagation delay), 47.95% (power-delay product (PDP)) improvement compared to the usual GDI implementation method. We used Microwind & Dsch Version 3.5 as well as the Tanner EDA 16.0 tools for simulation purposes.
Abstract: Digital signal processor, image signal processor and FIR filters have multipliers as an important part of their design. On the basis of Vedic mathematics, Vedic multipliers have come out to be very fast multipliers. One of the image processing applications is edge detection. This research presents a small area and high speed 8 bit Vedic multiplier system comprising of compressor based adders. This results in faster edge detection. This architecture is tested on Xilinx vertex 4 FPGA board and simulations were carried out using the Xilinx synthesis tool. Comparisons are made and this system is found to be smaller in area with high speed (the lesser propagation delay). This compressor based Vedic multiplier is 1.1 times speedier than a typical Vedic multiplier. Also, this Vedic Multiplier is 2 times speedier than a ‘simple’ multiplier.
Abstract: Data driven dynamic logic is the high speed dynamic circuit with low area. The clock of the dynamic circuit is removed and data drives the circuit instead of clock for precharging purpose. This data driven dynamic nand gate is given static forward substrate biasing of Vsupply/2 as well as the substrate bias is connected to the input data, resulting in dynamic substrate bias. The dynamic substrate bias gives the shortest propagation delay with a penalty on the power dissipation. Propagation delay is reduced by 77.8% compared to the normal reverse substrate bias Data driven dynamic nand. Also dynamic substrate biased D3nand’s propagation delay is reduced by 31.26% compared to data driven dynamic nand gate with static forward substrate biasing of Vdd/2. This data driven dynamic nand gate with dynamic body biasing gives us the highest speed with no area penalty and finds its applications where power penalty is acceptable. Also combination of Dynamic and static Forward body bias can be used with reduced propagation delay compared to static forward biased circuit and with comparable increase in an average power. The simulations were done on hspice simulator with 22nm High-k metal gate strained Si technology HP models of Arizona State University, USA.
Abstract: In this paper, the transient device performance analysis
of n-type Gate Inside JunctionLess Transistor (GI-JLT) has been
evaluated. 3-D Bohm Quantum Potential (BQP) transport device
simulation has been used to evaluate the delay and power dissipation
performance. GI-JLT has a number of desirable device parameters
such as reduced propagation delay, dynamic power dissipation,
power and delay product, intrinsic gate delay and energy delay
product as compared to Gate-all-around transistors GAA-JLT. In
addition to this, various other device performance parameters namely,
on/off current ratio, short channel effects (SCE), transconductance
Generation Factor (TGF) and unity gain cut-off frequency (fT ) and
subthreshold slope (SS) of the GI-JLT and GAA-JLT have been
analyzed and compared. GI-JLT shows better device performance
characteristics than GAA-JLT for low power and high frequency
applications, because of its larger gate electrostatic control on the
device operation.
Abstract: A modeling approach for CMOS gates is presented
based on the use of the equivalent inverter. A new model for the
inverter has been developed using a simplified transistor current
model which incorporates the nanoscale effects for the planar
technology. Parametric expressions for the output voltage are
provided as well as the values of the output and supply current to be
compatible with the CCS technology. The model is parametric
according the input signal slew, output load, transistor widths, supply
voltage, temperature and process. The transistor widths of the
equivalent inverter are determined by HSPICE simulations and
parametric expressions are developed for that using a fitting
procedure. Results for the NAND gate shows that the proposed
approach offers sufficient accuracy with an average error in
propagation delay about 5%.
Abstract: To develop the useful acoustic environmental
recognition system, the method of estimating 3D-position of a
stationary random acoustic source using bispectral analysis of
4-point detected signals is proposed. The method uses information
about amplitude attenuation and propagation delay extracted from
amplitude ratios and angles of auto- and cross-bispectra of the
detected signals. It is expected that using bispectral analysis affects
less influence of Gaussian noises than using conventional power
spectral one. In this paper, the basic principle of the method is
mentioned first, and its validity and features are considered from
results of the fundamental experiments assumed ideal circumstances.
Abstract: Minimizations of power dissipation, chip area with higher circuit performance are the necessary and key parameters in deep submicron regime. The leakage current increases sharply in deep submicron regime and directly affected the power dissipation of the logic circuits. In deep submicron region the power dissipation as well as high performance is the crucial concern since increasing importance of portable systems. Number of leakage reduction techniques employed to reduce the leakage current in deep submicron region but they have some trade-off to control the leakage current. ONOFIC approach gives an excellent agreement between power dissipation and propagation delay for designing the efficient CMOS logic circuits. In this article ONOFIC approach is compared with LECTOR technique and output results show that ONOFIC approach significantly reduces the power dissipation and enhance the speed of the logic circuits. The lower power delay product is the big outcome of this approach and makes it an influential leakage reduction technique.
Abstract: The impact of selective excitation of circular helical modes of graded-index fibers on its capacity is analyzed using a model for propagation delay variation with launch offset and angle that resulted from misalignment of source and fiber axis. Results show promising technique to improve graded-index fiber capacities.
Abstract: This paper presents CMOS Current Mode Logic (CML) circuits for a high speed Digital to Analog Converter (DAC) using standard CMOS 65nm process. The CML circuits have the propagation delay advantage over its conventional CMOS counterparts due to smaller output voltage swing and tunable bias current. The CML circuits proposed in this paper can achieve a maximum propagation delay of only 9.3ps, which can satisfy the stringent requirement for the 5 GHz high speed DAC application. Another advantage for CML circuits is its dynamic symmetry characteristic resulting in a reduction of an additional inverter. Simulation results show that the proposed CML circuits can operate from 1.08V to 1.3V with temperature ranging from -40 to +120°C.
Abstract: This paper describes the design of new method of
propagation delay measurement in micro and nanostructures during
characterization of ASIC standard library cell. Providing more
accuracy timing information about library cell to the design team we
can improve a quality of timing analysis inside of ASIC design flow
process. Also, this information could be very useful for semiconductor
foundry team to make correction in technology process. By
comparison of the propagation delay in the CMOS element and result
of analog SPICE simulation. It was implemented as digital IP core for
semiconductor manufacturing process. Specialized method helps to
observe the propagation time delay in one element of the standard-cell
library with up-to picoseconds accuracy and less. Thus, the special
useful solutions for VLSI schematic to parameters extraction, basic
cell layout verification, design simulation and verification are
announced.
Abstract: In this paper, a design methodology to implement low-power and high-speed 2nd order recursive digital Infinite Impulse Response (IIR) filter has been proposed. Since IIR filters suffer from a large number of constant multiplications, the proposed method replaces the constant multiplications by using addition/subtraction and shift operations. The proposed new 6T adder cell is used as the Carry-Save Adder (CSA) to implement addition/subtraction operations in the design of recursive section IIR filter to reduce the propagation delay. Furthermore, high-level algorithms designed for the optimization of the number of CSA blocks are used to reduce the complexity of the IIR filter. The DSCH3 tool is used to generate the schematic of the proposed 6T CSA based shift-adds architecture design and it is analyzed by using Microwind CAD tool to synthesize low-complexity and high-speed IIR filters. The proposed design outperforms in terms of power, propagation delay, area and throughput when compared with MUX-12T, MCIT-7T based CSA adder filter design. It is observed from the experimental results that the proposed 6T based design method can find better IIR filter designs in terms of power and delay than those obtained by using efficient general multipliers.
Abstract: The advancement in wireless technology with the wide
use of mobile devices have drawn the attention of the research and
technological communities towards wireless environments, such as
Wireless Local Area Networks (WLANs), Wireless Wide Area
Networks (WWANs), and mobile systems and ad-hoc networks.
Unfortunately, wired and wireless networks are expressively different
in terms of link reliability, bandwidth, and time of propagation delay
and by adapting new solutions for these enhanced
telecommunications, superior quality, efficiency, and opportunities
will be provided where wireless communications were otherwise
unfeasible. Some researchers define 4G as a significant improvement
of 3G, where current cellular network’s issues will be solved and data
transfer will play a more significant role. For others, 4G unifies
cellular and wireless local area networks, and introduces new routing
techniques, efficient solutions for sharing dedicated frequency bands,
and an increased mobility and bandwidth capacity. This paper
discusses the possible solutions and enhancements probabilities that
proposed to improve the performance of Transmission Control
Protocol (TCP) over different wireless networks and also the paper
investigated each approach in term of advantages and disadvantages.
Abstract: The resistive-inductive-capacitive behavior of long
interconnects which are driven by CMOS gates are presented in this
paper. The analysis is based on the ¤Ç-model of a RLC load and is
developed for submicron devices. Accurate and analytical
expressions for the output load voltage, the propagation delay and the
short circuit power dissipation have been proposed after solving a
system of differential equations which accurately describe the
behavior of the circuit. The effect of coupling capacitance between
input and output and the short circuit current on these performance
parameters are also incorporated in the proposed model. The
estimated proposed delay and short circuit power dissipation are in
very good agreement with the SPICE simulation with average
relative error less than 6%.
Abstract: The proposed multiplexer-based novel 1-bit full
adder cell is schematized by using DSCH2 and its layout is generated
by using microwind VLSI CAD tool. The adder cell layout
interconnect analysis is performed by using BSIM4 layout analyzer.
The adder circuit is compared with other six existing adder circuits
for parametric analysis. The proposed adder cell gives better
performance than the other existing six adder circuits in terms of
power, propagation delay and PDP. The proposed adder circuit is
further analyzed for interconnect analysis, which gives better
performance than other adder circuits in terms of layout thickness,
width and height.
Abstract: A reduced-bit multiplication algorithm based on the ancient Vedic multiplication formulae is proposed in this paper. Both the Vedic multiplication formulae, Urdhva tiryakbhyam and Nikhilam, are first discussed in detail. Urdhva tiryakbhyam, being a general multiplication formula, is equally applicable to all cases of multiplication. It is applied to the digital arithmetic and is shown to yield a multiplier architecture which is very similar to the popular array multiplier. Due to its structure, it leads to a high carry propagation delay in case of multiplication of large numbers. Nikhilam Sutra, on the other hand, is more efficient in the multiplication of large numbers as it reduces the multiplication of two large numbers to that of two smaller numbers. The framework of the proposed algorithm is taken from this Sutra and is further optimized by use of some general arithmetic operations such as expansion and bit-shifting to take advantage of bit-reduction in multiplication. We illustrate the proposed algorithm by reducing a general 4x4-bit multiplication to a single 2 x 2-bit multiplication operation.