Photovoltaic Array Sizing for PV-Electrolyzer

Hydrogen that used as fuel in fuel cell vehicles can be produced from renewable sources such as wind, solar, and hydro technologies. PV-electrolyzer is one of the promising methods to produce hydrogen with zero pollution emission. Hydrogen production from a PV-electrolyzer system depends on the efficiency of the electrolyzer and photovoltaic array, and sun irradiance at that site. In this study, the amount of hydrogen is obtained using mathematical equations for difference driving distance and sun peak hours. The results show that the minimum of 99 PV modules are used to generate 1.75 kgH2 per day for two vehicles.

A Fixed Band Hysteresis Current Controller for Voltage Source AC Chopper

Most high-performance ac drives utilize a current controller. The controller switches a voltage source inverter (VSI) such that the motor current follows a set of reference current waveforms. Fixed-band hysteresis (FBH) current control has been widely used for the PWM inverter. We want to apply the same controller for the PWM AC chopper. The aims of the controller is to optimize the harmonic content at both input and output sides, while maintaining acceptable losses in the ac chopper and to control in wide range the fundamental output voltage. Fixed band controller has been simulated and analyzed for a single-phase AC chopper and are easily extended to three-phase systems. Simulation confirmed the advantages and the excellent performance of the modulation method applied for the AC chopper.

Investigation of Titanium Oxide Layer in Thermal-Electrochemical Anodizing of Ti6Al4V Alloy

In this paper the combination of thermal oxidation and electrochemical anodizing processes is used to produce titanium oxide layers. The response of titanium alloy Ti6Al4V to oxidation processes at various temperatures and electrochemical anodizing in various voltages are investigated. Scanning electron microscopy (SEM); X-Ray Diffraction (XRD) and porosity determination have been used to characterize the oxide layer thickness, surface morphology, oxide layer-substrate adhesion and porosity. In the first experiment, samples modified by thermal oxidation process then followed by electrochemical anodizing. Second experiment consists of surfaces modified by electrochemical anodizing process and then followed by thermal oxidation. The first method shows better properties than other one. In second experiment, Surfaces modified were achieved by thicker and more adherent thick oxide layers on titanium surface. The existence of an electrochemical anodized oxide layer did not improve the adhesion of thermal oxide layer. The high temperature, thermal formation of an oxide layer leads to a coarse oxide grain morphology and a complete oxidative particle. In addition, in high temperature oxidation porosity content is increased. The oxide layer of thermal oxidation and electrochemical anodizing processes; on Ti–6Al–4V substrate was covered with different colored oxide layers.

Subthreshold Circuit Performance Investigation under Temperature Variations

Ultra-low-power (ULP) circuits have received widespread attention due to the rapid growth of biomedical applications and Battery-less Electronics. Subthreshold region of transistor operation is used in ULP circuits. Major research challenge in the subthreshold operating region is to extract the ULP benefits with minimal degradation in speed and robustness. Process, Voltage and Temperature (PVT) variations significantly affect the performance of subthreshold circuits. Designed performance parameters of ULP circuits may vary largely due to temperature variations. Hence, this paper investigates the effect of temperature variation on device and circuit performance parameters at different biasing voltages in the subthreshold region. Simulation results clearly demonstrate that in deep subthreshold and near threshold voltage regions, performance parameters are significantly affected whereas in moderate subthreshold region, subthreshold circuits are more immune to temperature variations. This establishes that moderate subthreshold region is ideal for temperature immune circuits.

Modeling and Analysis of SVPWM Based Dynamic Voltage Restorer

In this paper the modeling and analysis of Space Vector Pulse Width Modulation (SVPWM) based Dynamic Voltage Restorer (DVR) using PSCAD/EMTDC software will be presented in details. The simulation includes full modeling of the SVPWM technique used to control the DVR inverter. A test power system composed of three phase voltage source, sag generator, DVR and three phase resistive load is used to demonstrate restoration capability of the DVR. The simulation results of the presented DVR proved excellent voltage sag mitigation to protect sensitive loads.

Wavelet Entropy Based Algorithm for Fault Detection and Classification in FACTS Compensated Transmission Line

Distance protection of transmission lines including advanced flexible AC transmission system (FACTS) devices has been a very challenging task. FACTS devices of interest in this paper are static synchronous series compensators (SSSC) and unified power flow controller (UPFC). In this paper, a new algorithm is proposed to detect and classify the fault and identify the fault position in a transmission line with respect to a FACTS device placed in the midpoint of the transmission line. Discrete wavelet transformation and wavelet entropy calculations are used to analyze during fault current and voltage signals of the compensated transmission line. The proposed algorithm is very simple and accurate in fault detection and classification. A variety of fault cases and simulation results are introduced to show the effectiveness of such algorithm.

Screen of MicroRNA Targets in Zebrafish Using Heterogeneous Data Sources: A Case Study for Dre-miR-10 and Dre-miR-196

It has been established that microRNAs (miRNAs) play an important role in gene expression by post-transcriptional regulation of messengerRNAs (mRNAs). However, the precise relationships between microRNAs and their target genes in sense of numbers, types and biological relevance remain largely unclear. Dissecting the miRNA-target relationships will render more insights for miRNA targets identification and validation therefore promote the understanding of miRNA function. In miRBase, miRanda is the key algorithm used for target prediction for Zebrafish. This algorithm is high-throughput but brings lots of false positives (noise). Since validation of a large scale of targets through laboratory experiments is very time consuming, several computational methods for miRNA targets validation should be developed. In this paper, we present an integrative method to investigate several aspects of the relationships between miRNAs and their targets with the final purpose of extracting high confident targets from miRanda predicted targets pool. This is achieved by using the techniques ranging from statistical tests to clustering and association rules. Our research focuses on Zebrafish. It was found that validated targets do not necessarily associate with the highest sequence matching. Besides, for some miRNA families, the frequency of their predicted targets is significantly higher in the genomic region nearby their own physical location. Finally, in a case study of dre-miR-10 and dre-miR-196, it was found that the predicted target genes hoxd13a, hoxd11a, hoxd10a and hoxc4a of dre-miR- 10 while hoxa9a, hoxc8a and hoxa13a of dre-miR-196 have similar characteristics as validated target genes and therefore represent high confidence target candidates.

A 3.125Gb/s Clock and Data Recovery Circuit Using 1/4-Rate Technique

This paper describes the design and fabrication of a clock and data recovery circuit (CDR). We propose a new clock and data recovery which is based on a 1/4-rate frequency detector (QRFD). The proposed frequency detector helps reduce the VCO frequency and is thus advantageous for high speed application. The proposed frequency detector can achieve low jitter operation and extend the pull-in range without using the reference clock. The proposed CDR was implemented using a 1/4-rate bang-bang type phase detector (PD) and a ring voltage controlled oscillator (VCO). The CDR circuit has been fabricated in a standard 0.18 CMOS technology. It occupies an active area of 1 x 1 and consumes 90 mW from a single 1.8V supply.

Performance Enhancement of Dye-Sensitized Solar Cells by MgO Coating on TiO2 Electrodes

TiO2/MgO composite films were prepared by coating the magnesium acetate solution in the pores of mesoporous TiO2 films using a dip coating method. Concentrations of magnesium acetate solution were varied in a range of 1x10-4 – 1x10-1 M. The TiO2/MgO composite films were characterized by scanning electron microscopy (SEM), transmission electron microscropy (TEM), electrochemical impedance spectroscopy(EIS) , transient voltage decay and I-V test. The TiO2 films and TiO2/MgO composite films were immersed in a 0.3 mM N719 dye solution. The Dye-sensitized solar cells with the TiO2/MgO/N719 structure showed an optimal concentration of magnesium acetate solution of 1x10-3 M resulting in the MgO film estimated thickness of 0.0963 nm and giving the maximum efficiency of 4.85%. The improved efficiency of dyesensitized solar cell was due to the magnesium oxide film as the wide band gap coating decays the electron back transfer to the triiodide electrolyte and reduce charge recombination.

Stability of Functionally Graded Beams with Piezoelectric Layers Based on the First Order Shear Deformation Theory

Stability of functionally graded beams with piezoelectric layers subjected to axial compressive load that is simply supported at both ends is studied in this paper. The displacement field of beam is assumed based on first order shear deformation beam theory. Applying the Hamilton's principle, the governing equation is established. The influences of applied voltage, dimensionless geometrical parameter, functionally graded index and piezoelectric thickness on the critical buckling load of beam are presented. To investigate the accuracy of the present analysis, a compression study is carried out with a known data.

Power Reduction by Automatic Monitoring and Control System in Active Mode

This paper describes a novel monitoring scheme to minimize total active power in digital circuits depend on the demand frequency, by adjusting automatically both supply voltage and threshold voltages based on circuit operating conditions such as temperature, process variations, and desirable frequency. The delay monitoring results, will be control and apply so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. Design details of power monitor are examined using simulation framework in 32nm BTPM model CMOS process. Experimental results show the overhead of proposed circuit in terms of its power consumption is about 40 μW for 32nm technology; moreover the results show that our proposed circuit design is not far sensitive to the temperature variations and also process variations. Besides, uses the simple blocks which offer good sensitivity, high speed, the continuously feedback loop. This design provides up to 40% reduction in power consumption in active mode.

A New Method for Rapid DNA Extraction from Artemia (Branchiopoda, Crustacea)

Artemia is one of the most conspicuous invertebrates associated with aquaculture. It can be considered as a model organism, offering numerous advantages for comprehensive and multidisciplinary studies using morphologic or molecular methods. Since DNA extraction is an important step of any molecular experiment, a new and a rapid method of DNA extraction from adult Artemia was described in this study. Besides, the efficiency of this technique was compared with two widely used alternative techniques, namely Chelex® 100 resin and SDS-chloroform methods. Data analysis revealed that the new method is the easiest and the most cost effective method among the other methods which allows a quick and efficient extraction of DNA from the adult animal.

Electrical Properties of n-CdO/p-Si Heterojunction Diode Fabricated by Sol Gel

n-CdO/p-Si heterojunction diode was fabricated using sol-gel spin coating technique which is a low cost and easily scalable method for preparing of semiconductor films. The structural and morphological properties of CdO film were investigated. The X-ray diffraction (XRD) spectra indicated that the film was of polycrystalline nature. The scanning electron microscopy (SEM) images indicate that the surface morphology CdO film consists of the clusters formed with the coming together of the nanoparticles. The electrical characterization of Au/n-CdO/p–Si/Al heterojunction diode was investigated by current-voltage. The ideality factor of the diode was found to be 3.02 for room temperature. The reverse current of the diode strongly increased with illumination intensity of 100 mWcm-2 and the diode gave a maximum open circuit voltage Voc of 0.04 V and short-circuits current Isc of 9.92×10-9 A.

Neural Network Based Predictive DTC Algorithm for Induction Motors

In this paper, a Neural Network based predictive DTC algorithm is proposed .This approach is used as an alternative to classical approaches .An appropriate riate Feed - forward network is chosen and based on its value of derivative electromagnetic torque ; optimal stator voltage vector is determined to be applied to the induction motor (by inverter). Moreover, an appropriate torque and flux observer is proposed.

General Purpose Pulse Width Modulation Based Sliding Mode Controller for Buck DC-DC

This paper is a simple and systematic approaches to the design and analysis a pulse width modulation (PWM) based sliding mode controller for buck DC-DC Converters. Various aspects of the design, including the practical problems and the proposed solutions, are detailed. However, these control strategies can't compensate for large load current and input voltage variations. In this paper, a new control strategy by compromising both schemes advantages and avoiding their drawbacks is proposed, analyzed and simulated.

NSGA Based Optimal Volt / Var Control in Distribution System with Dispersed Generation

In this paper, a method based on Non-Dominated Sorting Genetic Algorithm (NSGA) has been presented for the Volt / Var control in power distribution systems with dispersed generation (DG). Genetic algorithm approach is used due to its broad applicability, ease of use and high accuracy. The proposed method is better suited for volt/var control problems. A multi-objective optimization problem has been formulated for the volt/var control of the distribution system. The non-dominated sorting genetic algorithm based method proposed in this paper, alleviates the problem of tuning the weighting factors required in solving the multi-objective volt/var control optimization problems. Based on the simulation studies carried out on the distribution system, the proposed scheme has been found to be simple, accurate and easy to apply to solve the multiobjective volt/var control optimization problem of the distribution system with dispersed generation.

Earth Grid Safety Consideration: Civil Upgrade Works for an Energised Substation

The demand on High voltage (HV) infrastructures is growing due to the corresponding growth in industries and population. Many areas are being developed and therefore require additional electrical power to comply with the demand. Substation upgrade is one of the rapid solutions to ensure the continuous supply of power to customers. This upgrade requires civil modifications to structures and fences. The civil work requires excavation and steel works that may create unsafe touch conditions. This paper presents a brief theoretical overview of the touch voltage inside and around substations and uses CDEGS software to simulate a case study.

Physical Parameters for Reliability Evaluation

This paper presents ageing experiments controlled by the evolution of junction parameters. The deterioration of the device is related to high injection effects which modified the transport mechanisms in the space charge region of the junction. Physical phenomena linked to the degradation of junction parameters that affect the devices reliability are reported and discussed. We have used the method based on numerical analysis of experimental current-voltage characteristic of the junction, in order to extract the electrical parameters. The simultaneous follow-up of the evolutions of the series resistance and of the transition voltage allow us to introduce a new parameter for reliability evaluation.

Improvement of Short Channel Effects in Cylindrical Strained Silicon Nanowire Transistor

In this paper we investigate the electrical characteristics of a new structure of gate all around strained silicon nanowire field effect transistors (FETs) with dual dielectrics by changing the radius (RSiGe) of silicon-germanium (SiGe) wire and gate dielectric. Indeed the effect of high-κ dielectric on Field Induced Barrier Lowering (FIBL) has been studied. Due to the higher electron mobility in tensile strained silicon, the n-type FETs with strained silicon channel have better drain current compare with the pure Si one. In this structure gate dielectric divided in two parts, we have used high-κ dielectric near the source and low-κ dielectric near the drain to reduce the short channel effects. By this structure short channel effects such as FIBL will be reduced indeed by increasing the RSiGe, ID-VD characteristics will be improved. The leakage current and transfer characteristics, the threshold-voltage (Vt), the drain induced barrier height lowering (DIBL), are estimated with respect to, gate bias (VG), RSiGe and different gate dielectrics. For short channel effects, such as DIBL, gate all around strained silicon nanowire FET have similar characteristics with the pure Si one while dual dielectrics can improve short channel effects in this structure.

An On-chip LDO Voltage Regulator with Improved Current Buffer Compensation

A fully on-chip low drop-out (LDO) voltage regulator with 100pF output load capacitor is presented. A novel frequency compensation scheme using current buffer is adopted to realize single dominant pole within the unit gain frequency of the regulation loop, the phase margin (PM) is at least 50 degree under the full range of the load current, and the power supply rejection (PSR) character is improved compared with conventional Miller compensation. Besides, the differentiator provides a high speed path during the load current transient. Implemented in 0.18μm CMOS technology, the LDO voltage regulator provides 100mA load current with a stable 1.8V output voltage consuming 80μA quiescent current.