Abstract: Data driven dynamic logic is the high speed dynamic circuit with low area. The clock of the dynamic circuit is removed and data drives the circuit instead of clock for precharging purpose. This data driven dynamic nand gate is given static forward substrate biasing of Vsupply/2 as well as the substrate bias is connected to the input data, resulting in dynamic substrate bias. The dynamic substrate bias gives the shortest propagation delay with a penalty on the power dissipation. Propagation delay is reduced by 77.8% compared to the normal reverse substrate bias Data driven dynamic nand. Also dynamic substrate biased D3nand’s propagation delay is reduced by 31.26% compared to data driven dynamic nand gate with static forward substrate biasing of Vdd/2. This data driven dynamic nand gate with dynamic body biasing gives us the highest speed with no area penalty and finds its applications where power penalty is acceptable. Also combination of Dynamic and static Forward body bias can be used with reduced propagation delay compared to static forward biased circuit and with comparable increase in an average power. The simulations were done on hspice simulator with 22nm High-k metal gate strained Si technology HP models of Arizona State University, USA.
Abstract: This research paper presents highly optimized barrel
shifter at 22nm Hi K metal gate strained Si technology node. This
barrel shifter is having a unique combination of static and dynamic
body bias which gives lowest power delay product. This power delay
product is compared with the same circuit at same technology node
with static forward biasing at ‘supply/2’ and also with normal reverse
substrate biasing and still found to be the lowest. The power delay
product of this barrel sifter is .39362X10-17J and is lowered by
approximately 78% to reference proposed barrel shifter at 32nm bulk
CMOS technology. Power delay product of barrel shifter at 22nm Hi
K Metal gate technology with normal reverse substrate bias is
2.97186933X10-17J and can be compared with this design’s PDP of
.39362X10-17J. This design uses both static and dynamic substrate
biasing and also has approximately 96% lower power delay product
compared to only forward body biased at half of supply voltage. The
NMOS model used are predictive technology models of Arizona state
university and the simulations to be carried out using HSPICE
simulator.
Abstract: In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling. Recently, the power density has increased due to combination of higher clock speeds, greater functional integration, and smaller process geometries. As a result static power consumption is becoming more dominant. This is a challenge for the circuit designers. However, the designers do have a few methods which they can use to reduce this static power consumption. But all of these methods have some drawbacks. In order to achieve lower static power consumption, one has to sacrifice design area and circuit performance. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using Variable Body Biasing technique without being penalized in area requirement and circuit performance.
Abstract: This paper describes a novel monitoring scheme to
minimize total active power in digital circuits depend on the demand
frequency, by adjusting automatically both supply voltage and
threshold voltages based on circuit operating conditions such as
temperature, process variations, and desirable frequency. The delay
monitoring results, will be control and apply so as to be maintained at
the minimum value at which the chip is able to operate for a given
clock frequency. Design details of power monitor are examined using
simulation framework in 32nm BTPM model CMOS process.
Experimental results show the overhead of proposed circuit in terms
of its power consumption is about 40 μW for 32nm technology;
moreover the results show that our proposed circuit design is not far
sensitive to the temperature variations and also process variations.
Besides, uses the simple blocks which offer good sensitivity, high
speed, the continuously feedback loop. This design provides up to
40% reduction in power consumption in active mode.