Power Reduction by Automatic Monitoring and Control System in Active Mode
This paper describes a novel monitoring scheme to
minimize total active power in digital circuits depend on the demand
frequency, by adjusting automatically both supply voltage and
threshold voltages based on circuit operating conditions such as
temperature, process variations, and desirable frequency. The delay
monitoring results, will be control and apply so as to be maintained at
the minimum value at which the chip is able to operate for a given
clock frequency. Design details of power monitor are examined using
simulation framework in 32nm BTPM model CMOS process.
Experimental results show the overhead of proposed circuit in terms
of its power consumption is about 40 μW for 32nm technology;
moreover the results show that our proposed circuit design is not far
sensitive to the temperature variations and also process variations.
Besides, uses the simple blocks which offer good sensitivity, high
speed, the continuously feedback loop. This design provides up to
40% reduction in power consumption in active mode.
[1] N. Mehta, B. Amrutur, and P. M. Grant, "Dynamic supply and threshold
voltage scaling for CMOS digital circuits using in-situ power monitor
(Periodical styleÔÇöAccepted for publication)," IEEE Transactions on
very large scale integration (VLSI) systems, to be published.
[2] H. Jeon, Y. Bin Kim and M. Choi "Standby leakage power reduction
technique for nanoscale CMOS VLSI systems," IEEE Trans.
instrumentation and measurement, Vol. 59, No. 5, May 2010.
[3] N. Mehta, G. Naik, and B.Amrutur, "In-situ power monitoring scheme
and its application in dynamic voltage and threshold scaling for digital
CMOS integrated circuits," ISLPED-10, pp. 259-264, August 2010.
[4] A. Sathanur, A. Pullini, L. Benini, G. De Micheli, and E. Macii,
"Physically clustered forward body biasing for variability compensation
in nanometer CMOS design," EDAA, 2009.
[5] X. He, S. Al-Kadry, and A. Abdollahi "Adaptive leakage control on
body biasing for reducing power consumption in CMOS VLSI circuit,"
IEEE, 10th Int'l Symposium on Quality Electronic Design, pp. 465-470,
2009.
[6] H. Su, H. Wang, T. Xu, and R. Zeng "Effects of forward body bias on
high-frequency noise in 0.18-um CMOS transistors," IEEE Trans. on
microwave theory and techniques, VOL. 57, NO. 4, pp. 972-979, Apr.
2009
[7] K. K. Kim and Y. B. Kim, "A novel adaptive design methodology for
minimum leakage power considering PVT variations on nanoscale VLSI
systems," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 17,
No. 4, pp. 517-528, Apr. 2009.
[8] V. Khandelwal, A. Srivastava, "Active mode leakage reduction using
fine-grained forward body biasing strategy", Integration the VLSI
Journal, Vol. 40, No. 4, pp. 561-570, July 2007.
[9] M. Nomura, Y. Ikenaga, K. Takeda, Y. Nakazawa, Y. Aimoto, and Y.
Hagihara, "Delay and power monitoring schemes for minimizing power
consumption by means of supply and threshold voltage control in active
and standby modes," IEEE J. Solid-State Circuits, vol. 41, no. 4, pp.
805- 814, Apr. 2006.
[10] M. Nomura, Y. Ikenaga, K. Takeda, Y. Nakazawa, Y. Aimoto, and Y.
Hagihara, "Monitoring scheme for minimizing power consumption by
means of supply and threshold voltage control in active and standby
modes," in Symp. VLSI Circuits Dig. Tech. Papers, pp. 308-311, Jun.
2005.
[11] B. Zhai, D. Blaauw, D. Sylvester, and K. Flautner "Theoretical and
practical limits of dynamic voltage scaling," DAC, pp. 868-873,June
2004.
[12] C. Neau and K. Roy, "Optimal body bias selection for leakage
improvement and process compensation over different technology
generations," in Proc. ISLEP, pp. 116-121, Aug. 2003.
[13] T. Kao, M. Miyazaki, and P. Chandrakasan, "A 175-mv multiplyaccumulate
unit using an adaptive supply voltage and body bias
architecture," IEEE journal of solid-state circuits, vol. 37, no. 11, pp.
1545-1554, Nov. 2002.
[14] S. Abdollahi pour, and M. Saneei, "Off-state leakage power reduction by
automatic monitoring and control system," ICECECE. Accepted for
publication. 2011.
[15] H. Mostafa, M. Anis, and M. Elmasry, "Comparative analysis of timing
yield improvement under process variations of flip-flops circuits," IEEE
Computer society annual symposium on VLSI, pp. 133- 138, 2009.
[1] N. Mehta, B. Amrutur, and P. M. Grant, "Dynamic supply and threshold
voltage scaling for CMOS digital circuits using in-situ power monitor
(Periodical styleÔÇöAccepted for publication)," IEEE Transactions on
very large scale integration (VLSI) systems, to be published.
[2] H. Jeon, Y. Bin Kim and M. Choi "Standby leakage power reduction
technique for nanoscale CMOS VLSI systems," IEEE Trans.
instrumentation and measurement, Vol. 59, No. 5, May 2010.
[3] N. Mehta, G. Naik, and B.Amrutur, "In-situ power monitoring scheme
and its application in dynamic voltage and threshold scaling for digital
CMOS integrated circuits," ISLPED-10, pp. 259-264, August 2010.
[4] A. Sathanur, A. Pullini, L. Benini, G. De Micheli, and E. Macii,
"Physically clustered forward body biasing for variability compensation
in nanometer CMOS design," EDAA, 2009.
[5] X. He, S. Al-Kadry, and A. Abdollahi "Adaptive leakage control on
body biasing for reducing power consumption in CMOS VLSI circuit,"
IEEE, 10th Int'l Symposium on Quality Electronic Design, pp. 465-470,
2009.
[6] H. Su, H. Wang, T. Xu, and R. Zeng "Effects of forward body bias on
high-frequency noise in 0.18-um CMOS transistors," IEEE Trans. on
microwave theory and techniques, VOL. 57, NO. 4, pp. 972-979, Apr.
2009
[7] K. K. Kim and Y. B. Kim, "A novel adaptive design methodology for
minimum leakage power considering PVT variations on nanoscale VLSI
systems," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 17,
No. 4, pp. 517-528, Apr. 2009.
[8] V. Khandelwal, A. Srivastava, "Active mode leakage reduction using
fine-grained forward body biasing strategy", Integration the VLSI
Journal, Vol. 40, No. 4, pp. 561-570, July 2007.
[9] M. Nomura, Y. Ikenaga, K. Takeda, Y. Nakazawa, Y. Aimoto, and Y.
Hagihara, "Delay and power monitoring schemes for minimizing power
consumption by means of supply and threshold voltage control in active
and standby modes," IEEE J. Solid-State Circuits, vol. 41, no. 4, pp.
805- 814, Apr. 2006.
[10] M. Nomura, Y. Ikenaga, K. Takeda, Y. Nakazawa, Y. Aimoto, and Y.
Hagihara, "Monitoring scheme for minimizing power consumption by
means of supply and threshold voltage control in active and standby
modes," in Symp. VLSI Circuits Dig. Tech. Papers, pp. 308-311, Jun.
2005.
[11] B. Zhai, D. Blaauw, D. Sylvester, and K. Flautner "Theoretical and
practical limits of dynamic voltage scaling," DAC, pp. 868-873,June
2004.
[12] C. Neau and K. Roy, "Optimal body bias selection for leakage
improvement and process compensation over different technology
generations," in Proc. ISLEP, pp. 116-121, Aug. 2003.
[13] T. Kao, M. Miyazaki, and P. Chandrakasan, "A 175-mv multiplyaccumulate
unit using an adaptive supply voltage and body bias
architecture," IEEE journal of solid-state circuits, vol. 37, no. 11, pp.
1545-1554, Nov. 2002.
[14] S. Abdollahi pour, and M. Saneei, "Off-state leakage power reduction by
automatic monitoring and control system," ICECECE. Accepted for
publication. 2011.
[15] H. Mostafa, M. Anis, and M. Elmasry, "Comparative analysis of timing
yield improvement under process variations of flip-flops circuits," IEEE
Computer society annual symposium on VLSI, pp. 133- 138, 2009.
@article{"International Journal of Electrical, Electronic and Communication Sciences:52441", author = "Somaye Abdollahi Pour and Mohsen Saneei", title = "Power Reduction by Automatic Monitoring and Control System in Active Mode", abstract = "This paper describes a novel monitoring scheme to
minimize total active power in digital circuits depend on the demand
frequency, by adjusting automatically both supply voltage and
threshold voltages based on circuit operating conditions such as
temperature, process variations, and desirable frequency. The delay
monitoring results, will be control and apply so as to be maintained at
the minimum value at which the chip is able to operate for a given
clock frequency. Design details of power monitor are examined using
simulation framework in 32nm BTPM model CMOS process.
Experimental results show the overhead of proposed circuit in terms
of its power consumption is about 40 μW for 32nm technology;
moreover the results show that our proposed circuit design is not far
sensitive to the temperature variations and also process variations.
Besides, uses the simple blocks which offer good sensitivity, high
speed, the continuously feedback loop. This design provides up to
40% reduction in power consumption in active mode.", keywords = "active mode, delay monitor, body biasing, VDD
scaling, low power.", volume = "6", number = "1", pages = "40-6", }
