Improvement of Short Channel Effects in Cylindrical Strained Silicon Nanowire Transistor
In this paper we investigate the electrical
characteristics of a new structure of gate all around strained silicon
nanowire field effect transistors (FETs) with dual dielectrics by
changing the radius (RSiGe) of silicon-germanium (SiGe) wire and
gate dielectric. Indeed the effect of high-κ dielectric on Field Induced
Barrier Lowering (FIBL) has been studied. Due to the higher electron
mobility in tensile strained silicon, the n-type FETs with strained
silicon channel have better drain current compare with the pure Si
one. In this structure gate dielectric divided in two parts, we have
used high-κ dielectric near the source and low-κ dielectric near the
drain to reduce the short channel effects. By this structure short
channel effects such as FIBL will be reduced indeed by increasing
the RSiGe, ID-VD characteristics will be improved. The leakage
current and transfer characteristics, the threshold-voltage (Vt), the
drain induced barrier height lowering (DIBL), are estimated with
respect to, gate bias (VG), RSiGe and different gate dielectrics. For
short channel effects, such as DIBL, gate all around strained silicon
nanowire FET have similar characteristics with the pure Si one while
dual dielectrics can improve short channel effects in this structure.
[1] H.M. Nayfeh et al., "Influence of high channel doping on the inversion
layer electron mobility in strained silicon n-MOSFETs," IEEE Elec.
Dev. Lett., 24, 248 (2003).
[2] B.H. Lee et al., "Performance enhancement on sub-70 nm strained
silicon SOI MOSFETs on ultra-thin thermally mixed strained
silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D," Tech.
Dig. IEDM 946 (2002).
[3] C. Fenouillet-Beranger et al., "Requirements for ultra-thin-film devices
and new materials for the CMOS roadmap," Solid-State Elec., 48, 961
(2004).
[4] K. Rim et al., "Fabrication and analysis of deep submicron strained-Si n-
MOSFET-s," IEEE Trans. Elec. Dev., 47, 1406 (2000).
[5] L. Huang et al., "Electron and hole mobility enhancement in strained
SOI by wafer bonding," IEEE Trans. Elec. Dev., 49, 1566 (2002).
[6] J.R. Hwang et al., "Performance of 70 nm strained-silicon CMOS
devices," Dig. Tech. 2003 Symp. VLSI Tech., 103 (2003).
[7] J.Wang, E. Polizzi, M. Lundstrom, A three-dimensional quantum
simulation of silicon nanowire transistors with the effective-mass
approximation,J. Appl. Phys. 96 (2004) 2192-2203.
[8] R. Venugopal et al., "Simulating quantum transport in nanoscale
transistors: Real versus mode-space approaches," J. App. Phys., 92, 3730
(2002).
[9] J.Wang et al., "Does source-to-drain tunneling limit the ultimate scaling
of MOSFETs?," Tech. Dig. IEDM, 707 (2002).
[10] A. Svizhenko et al., "Role of scattering in nanotransistors," IEEE Trans.
Elec. Dev., 50, 1459 (2003).
[11] H. Kawaura et al., "Observation of source-to-drain direct tunneling
current in 8 nmgate electrically variable shallow junction metal-oxidesemiconductor
field-effect transistors," Appl. Phys. Lett., 76, 3810
(2000).
[12] M. Rashed et al., "Simulation of electron transport in strained silicon on
relaxed Si1−xGex substrates," in Proc. Biennial University/
Government/Industry Microelec. Symp. (1995) vol. 168.
[13] A. Schenk et al., "2D Analysis of source-to-drain tunneling in
decananometer MOSFETs with the density-gradient model," in Proc. 5th
Int. Conf. Modeling and Simulation of Microsystems, ed. M. laudon and
B. Romanowicz,pp.552-555,San Juan, 2002.
[14] S.N. Balaban et al., "Quantum transport in a cylindrical sub- 0.1 ╬╝m
silicon-based MOSFET," Solid-State Elec., 46, 435 (2002).
[15] X. Loussier, D. Munteanu, J.L. Autran Journal of Non-Crystalline Solids
355 (2009) 1185-1188.
[16] M. Houssa (Ed.), Fundamental and Technological Aspects of High-j
Gate Dielectrics, IOP, London, 2004.
[17] M. Houssa et al., MRS Symp. Proc. 177 (2004).
[18] B. Cheng et al., IEEE Trans. Electr. Dev. 46 (2003) 1537.
[19] YIMING LI, JAM-WEM LEE, Journal of Computational Electronics 3:
251-255, 2004.
[20] Silvaco International, Atlas User-s Manual, 2008.
[1] H.M. Nayfeh et al., "Influence of high channel doping on the inversion
layer electron mobility in strained silicon n-MOSFETs," IEEE Elec.
Dev. Lett., 24, 248 (2003).
[2] B.H. Lee et al., "Performance enhancement on sub-70 nm strained
silicon SOI MOSFETs on ultra-thin thermally mixed strained
silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D," Tech.
Dig. IEDM 946 (2002).
[3] C. Fenouillet-Beranger et al., "Requirements for ultra-thin-film devices
and new materials for the CMOS roadmap," Solid-State Elec., 48, 961
(2004).
[4] K. Rim et al., "Fabrication and analysis of deep submicron strained-Si n-
MOSFET-s," IEEE Trans. Elec. Dev., 47, 1406 (2000).
[5] L. Huang et al., "Electron and hole mobility enhancement in strained
SOI by wafer bonding," IEEE Trans. Elec. Dev., 49, 1566 (2002).
[6] J.R. Hwang et al., "Performance of 70 nm strained-silicon CMOS
devices," Dig. Tech. 2003 Symp. VLSI Tech., 103 (2003).
[7] J.Wang, E. Polizzi, M. Lundstrom, A three-dimensional quantum
simulation of silicon nanowire transistors with the effective-mass
approximation,J. Appl. Phys. 96 (2004) 2192-2203.
[8] R. Venugopal et al., "Simulating quantum transport in nanoscale
transistors: Real versus mode-space approaches," J. App. Phys., 92, 3730
(2002).
[9] J.Wang et al., "Does source-to-drain tunneling limit the ultimate scaling
of MOSFETs?," Tech. Dig. IEDM, 707 (2002).
[10] A. Svizhenko et al., "Role of scattering in nanotransistors," IEEE Trans.
Elec. Dev., 50, 1459 (2003).
[11] H. Kawaura et al., "Observation of source-to-drain direct tunneling
current in 8 nmgate electrically variable shallow junction metal-oxidesemiconductor
field-effect transistors," Appl. Phys. Lett., 76, 3810
(2000).
[12] M. Rashed et al., "Simulation of electron transport in strained silicon on
relaxed Si1−xGex substrates," in Proc. Biennial University/
Government/Industry Microelec. Symp. (1995) vol. 168.
[13] A. Schenk et al., "2D Analysis of source-to-drain tunneling in
decananometer MOSFETs with the density-gradient model," in Proc. 5th
Int. Conf. Modeling and Simulation of Microsystems, ed. M. laudon and
B. Romanowicz,pp.552-555,San Juan, 2002.
[14] S.N. Balaban et al., "Quantum transport in a cylindrical sub- 0.1 ╬╝m
silicon-based MOSFET," Solid-State Elec., 46, 435 (2002).
[15] X. Loussier, D. Munteanu, J.L. Autran Journal of Non-Crystalline Solids
355 (2009) 1185-1188.
[16] M. Houssa (Ed.), Fundamental and Technological Aspects of High-j
Gate Dielectrics, IOP, London, 2004.
[17] M. Houssa et al., MRS Symp. Proc. 177 (2004).
[18] B. Cheng et al., IEEE Trans. Electr. Dev. 46 (2003) 1537.
[19] YIMING LI, JAM-WEM LEE, Journal of Computational Electronics 3:
251-255, 2004.
[20] Silvaco International, Atlas User-s Manual, 2008.
@article{"International Journal of Electrical, Electronic and Communication Sciences:52244", author = "Fatemeh Karimi and Morteza Fathipour and Hamdam Ghanatian and Vala Fathipour", title = "Improvement of Short Channel Effects in Cylindrical Strained Silicon Nanowire Transistor", abstract = "In this paper we investigate the electrical
characteristics of a new structure of gate all around strained silicon
nanowire field effect transistors (FETs) with dual dielectrics by
changing the radius (RSiGe) of silicon-germanium (SiGe) wire and
gate dielectric. Indeed the effect of high-κ dielectric on Field Induced
Barrier Lowering (FIBL) has been studied. Due to the higher electron
mobility in tensile strained silicon, the n-type FETs with strained
silicon channel have better drain current compare with the pure Si
one. In this structure gate dielectric divided in two parts, we have
used high-κ dielectric near the source and low-κ dielectric near the
drain to reduce the short channel effects. By this structure short
channel effects such as FIBL will be reduced indeed by increasing
the RSiGe, ID-VD characteristics will be improved. The leakage
current and transfer characteristics, the threshold-voltage (Vt), the
drain induced barrier height lowering (DIBL), are estimated with
respect to, gate bias (VG), RSiGe and different gate dielectrics. For
short channel effects, such as DIBL, gate all around strained silicon
nanowire FET have similar characteristics with the pure Si one while
dual dielectrics can improve short channel effects in this structure.", keywords = "SNWT (silicon nanowire transistor), Tensile Strain,high-κ dielectric, Field Induced Barrier Lowering (FIBL), cylindricalnano wire (CW), drain induced barrier lowering (DIBL).", volume = "4", number = "9", pages = "1344-4", }