Abstract: This work is a proposed model of CMOS for which
the algorithm has been created and then the performance evaluation
of this proposition has been done. In this context, another commonly
used model called ZSTT (Zero Switching Time Transient) model is
chosen to compare all the vital features and the results for the
Proposed Equivalent CMOS are promising. In the end, the excerpts
of the created algorithm are also included
Abstract: This article proposes a current-mode square-rooting
circuit using current follower transconductance amplifier (CTFA).
The amplitude of the output current can be electronically controlled
via input bias current with wide input dynamic range. The proposed
circuit consists of only single CFTA. Without any matching
conditions and external passive elements, the circuit is then
appropriate for an IC architecture. The magnitude of the output signal
is temperature-insensitive. The PSpice simulation results are
depicted, and the given results agree well with the theoretical
anticipation. The power consumption is approximately 1.96mW at
±1.5V supply voltages.
Abstract: A fast settling multipath CMOS OTA for high speed
switched capacitor applications is presented here. With the basic
topology similar to folded-cascode, bandwidth and DC gain of the
OTA are enhanced by adding extra paths for signal from input to
output. Designed circuit is simulated with HSPICE using level 49
parameters (BSIM 3v3) in 0.35mm standard CMOS technology. DC
gain achieved is 56.7dB and Unity Gain Bandwidth (UGB) obtained
is 1.15GHz. These results confirm that adding extra paths for signal
can improve DC gain and UGB of folded-cascode significantly.
Abstract: In this paper a novel high output impedance, low input impedance, wide bandwidth, very simple current mirror with input and output voltage requirements less than that of a simple current mirror is presented. These features are achieved with very simple structure avoiding extra large node impedances to ensure high bandwidth operation. The circuit's principle of operation is discussed and compared to simple and low voltage cascode (LVC) current mirrors. Such outstanding features of this current mirror as high output impedance ~384K, low input impedance~6.4, wide bandwidth~178MHz, low input voltage ~ 362mV, low output voltage ~ 38mV and low current transfer error ~4% (all at 50μA) makes it an outstanding choice for high performance applications. Simulation results in BSIM 0.35μm CMOS technology with HSPICE are given in comparison with simple, and LVC current mirrors to verify and validate the performance of the proposed current mirror.
Abstract: Since 2004, we have been developing an in-situ storage image sensor (ISIS) that captures more than 100 consecutive images at a frame rate of 10 Mfps with ultra-high sensitivity as well as the video camera for use with this ISIS. Currently, basic research is continuing in an attempt to increase the frame rate up to 100 Mfps and above. In order to suppress electro-magnetic noise at such high frequency, a digital-noiseless imaging transfer scheme has been developed utilizing solely sinusoidal driving voltages. This paper presents highly efficient-yet-accurate expressions to estimate attenuation as well as phase delay of driving voltages through RC networks of an ultra-high-speed image sensor. Elmore metric for a fundamental RC chain is employed as the first-order approximation. By application of dimensional analysis to SPICE data, we found a simple expression that significantly improves the accuracy of the approximation. Similarly, another simple closed-form model to estimate phase delay through fundamental RC networks is also obtained. Estimation error of both expressions is much less than previous works, only less 2% for most of the cases . The framework of this analysis can be extended to address similar issues of other VLSI structures.
Abstract: Saffron (Crocus sativus) is cultivated as spices,
medicinal and aromatic plant species. At autumn season, heavy
rainfall can cause flooding stress and inhibits growth of saffron. Thus
this research was conducted to study the effect of silver ion (as an
ethylene inhibitor) on growth of saffron under flooding conditions.
The corms of saffron were soaked with one concentration of nano
silver (0, 40, 80 or 120 ppm) and then planting under flooding stress
or non flooding stress conditions. Results showed that number of
roots, root length, root fresh and dry weight, leaves fresh and dry
weight were reduced by 10 day flooding stress. Soaking saffron
corms with 40 or 80 ppm concentration of nano silver rewarded the
effect of flooding stress on the root number, by increasing it.
Furthermore, 40 ppm of nano silver increased root length in stress.
Nano silver 80 ppm in flooding stress, increased leaves dry weight.
Abstract: This paper presents the design of a low power second-order continuous-time sigma-delta modulator for low power
applications. The loop filter of this modulator has been implemented based on the nonlinear transconductance-capacitor (Gm-C) by employing current-mode technique. The nonlinear transconductance uses floating gate MOS (FG-MOS) transistors that operate in weak inversion region. The proposed modulator features low power consumption (
Abstract: We have fabricated a-IGZO TFT and investigated the
stability under positive DC and AC bias stress. The threshold voltage
of a-IGZO TFT shifts positively under those biases, and that reduces
on-current. For this reason, conventional shift-register circuit
employing TFTs which stressed by positive bias will be unstable, may
do not work properly. We have designed a new 6-transistor
shift-register, which has less transistors than prior circuits. The TFTs
of the proposed shift-register are not suffering from positive DC or AC
stress, mainly kept unbiased. Despite the compact design, the stable
output signal was verified through the SPICE simulation even under
RC delay of clock signal.
Abstract: A novel three-phase active power filter (APF) circuit with photovoltaic (PV) system to improve the quality of service and to reduce the capacity of energy storage capacitor is presented. The energy balance concept and sampling technique were used to simplify the calculation algorithm for the required utility source current and to control the voltage of the energy storage capacitor. The feasibility was verified by using the Pspice simulations and experiments. When the APF mode was used during non-operational period, not only the utilization rate, power factor and power quality could be improved, but also the capacity of energy storage capacitor could sparing. As the results, the advantages of the APF circuit are simplicity of control circuits, low cost, and good transient response.
Abstract: A new OTA-based logarithmic-control variable gain
current amplifier (LCCA) is presented. It consists of two Operational
Transconductance Amplifier (OTA) and two PMOS transistors
biased in weak inversion region. The circuit operates from 0.6V DC
power supply and consumes 0.6 μW. The linear-dB controllable
output range is 43 dB with maximum error less than 0.5dB. The
functionality of the proposed design was confirmed using HSPICE in
0.35μm CMOS process technology.
Abstract: In this paper, based on a novel synthesis, a set of new simplified circuit design to implement the linguistic-hedge operations for adjusting the fuzzy membership function set is presented. The circuits work in current-mode and employ floating-gate MOS (FGMOS) transistors that operate in weak inversion region. Compared to the other proposed circuits, these circuits feature severe reduction of the elements number, low supply voltage (0.7V), low power consumption (60dB). In this paper, a set of fuzzy linguistic hedge circuits, including absolutely, very, much more, more, plus minus, more or less and slightly, has been implemented in 0.18 mm CMOS process. Simulation results by Hspice confirm the validity of the proposed design technique and show high performance of the circuits.
Abstract: New methodologies for XOR-XNOR circuits are
proposed to improve the speed and power as these circuits are basic
building blocks of many arithmetic circuits. This paper evaluates and
compares the performance of various XOR-XNOR circuits. The
performance of the XOR-XNOR circuits based on TSMC 0.18μm
process models at all range of the supply voltage starting from 0.6V
to 3.3V is evaluated by the comparison of the simulation results
obtained from HSPICE. Simulation results reveal that the proposed
circuit exhibit lower PDP and EDP, more power efficient and faster
when compared with best available XOR-XNOR circuits in the
literature.
Abstract: We present an explicit expression to estimate driving voltage attenuation through RC networks representation of an ultrahigh- speed image sensor. Elmore delay metric for a fundamental RC chain is employed as the first-order approximation. By application of dimensional analysis to SPICE simulation data, we found a simple expression that significantly improves the accuracy of the approximation. Estimation error of the resultant expression for uniform RC networks is less than 2%. Similarly, another simple closed-form model to estimate 50 % delay through fundamental RC networks is also derived with sufficient accuracy. The framework of this analysis can be extended to address delay or attenuation issues of other VLSI structures.
Abstract: This paper presents an adaptive technique for generation
of data required for construction of artificial neural network-based
performance model of nano-scale CMOS inverter circuit. The training
data are generated from the samples through SPICE simulation. The
proposed algorithm has been compared to standard progressive sampling
algorithms like arithmetic sampling and geometric sampling.
The advantages of the present approach over the others have been
demonstrated. The ANN predicted results have been compared with
actual SPICE results. A very good accuracy has been obtained.
Abstract: This article presents a current-mode universal biquadratic filter. The proposed circuit can apparently provide standard functions of the biquad filter: low-pass, high-pass, bandpass, band-reject and all-pass functions. The circuit uses 4 current controlled transconductance amplifiers (CCTAs) and 2 grounded capacitors. In addition, the pole frequency and quality factor can be adjusted by electronic method by adjusting the bias currents of the CCTA. The proposed circuit uses only grounded capacitors without additional external resistors, the proposed circuit is considerably appropriate to further developing into an integrated circuit. The results of PSPICE simulation program are corresponding to the theoretical analysis.
Abstract: A new low-voltage floating gate MOSFET (FGMOS)
based squarer using square law characteristic of the FGMOS is
proposed in this paper. The major advantages of the squarer are simplicity,
rail-to-rail input dynamic range, low total harmonic distortion,
and low power consumption. The proposed circuit is biased without
body effect. The circuit is designed and simulated using SPICE in
0.25μm CMOS technology. The squarer is operated at the supply
voltages of ±0.75V . The total harmonic distortion (THD) for the
input signal 0.75Vpp at 25 KHz, and maximum power consumption
were found to be less than 1% and 319μW respectively.
Abstract: The energy consumption and delay in read/write
operation of conventional SRAM is investigated analytically as well
as by simulation. Explicit analytical expressions for the energy
consumption and delay in read and write operation as a function of
device parameters and supply voltage are derived. The expressions are
useful in predicting the effect of parameter changes on the energy
consumption and speed as well as in optimizing the design of
conventional SRAM. HSPICE simulation in standard 0.25μm CMOS
technology confirms precision of analytical expressions derived from
this paper.
Abstract: Each new semiconductor technology node
brings smaller transistors and wires. Although this makes
transistors faster, wires get slower. In nano-scale regime, the
standard copper (Cu) interconnect will become a major hurdle
for FPGA interconnect due to their high resistivity and
electromigration. This paper presents the comprehensive
evaluation of mixed CNT bundle interconnects and
investigates their prospects as energy efficient and high speed
interconnect for future FPGA routing architecture. All
HSPICE simulations are carried out at operating frequency of
1GHz and it is found that mixed CNT bundle implemented in
FPGAs as interconnect can potentially provide a substantial
delay and energy reduction over traditional interconnects at
32nm process technology.
Abstract: A new current-mode multifunction filter using minimum number of passive elements is proposed. The proposed filter has single-input and four high-impedance outputs. It uses four passive elements (two capacitors and two resistors) and four dual output second generation current conveyors. Each output provides a different filter response, namely, low-pass, high-pass, band-pass and band-reject. The sensitivity analysis is also carried out on both ideal and non-ideal filter configurations. The validity of the proposed filter is verified through PSPICE simulations.