Delay and Energy Consumption Analysis of Conventional SRAM
The energy consumption and delay in read/write
operation of conventional SRAM is investigated analytically as well
as by simulation. Explicit analytical expressions for the energy
consumption and delay in read and write operation as a function of
device parameters and supply voltage are derived. The expressions are
useful in predicting the effect of parameter changes on the energy
consumption and speed as well as in optimizing the design of
conventional SRAM. HSPICE simulation in standard 0.25μm CMOS
technology confirms precision of analytical expressions derived from
this paper.
[1] S. P. Cheng, S. Y. Huang "A Low-Power SRAM Design Using Quiet-
Bitline Architecture" Proc. of IEEE Int-l Workshop on Memory
Technology Design and Testing, 2005.
[2] A. Karandikar and K. K. Parhi, "Low power SRAM design using
hierarchical divided bit-line approach," in Proc. Int. Conf. Computer
Design: VLSI in Computers and Processors, 1998, pp. 82-88.
[3] B. D. Yang, L. S. Kim, "A Low-Power SRAM Using Hierarchical Bit
Line and Local Sense Amplifiers" IEEE J. Solid State Circuits, Vol. 40,
pp. 1366-1376, June 2005.
[4] J. K. Martin "Digital Integrated Circuit Design" Oxford University Press,
New York, 2000, pp. 180-182.
[1] S. P. Cheng, S. Y. Huang "A Low-Power SRAM Design Using Quiet-
Bitline Architecture" Proc. of IEEE Int-l Workshop on Memory
Technology Design and Testing, 2005.
[2] A. Karandikar and K. K. Parhi, "Low power SRAM design using
hierarchical divided bit-line approach," in Proc. Int. Conf. Computer
Design: VLSI in Computers and Processors, 1998, pp. 82-88.
[3] B. D. Yang, L. S. Kim, "A Low-Power SRAM Using Hierarchical Bit
Line and Local Sense Amplifiers" IEEE J. Solid State Circuits, Vol. 40,
pp. 1366-1376, June 2005.
[4] J. K. Martin "Digital Integrated Circuit Design" Oxford University Press,
New York, 2000, pp. 180-182.
@article{"International Journal of Electrical, Electronic and Communication Sciences:57492", author = "Arash Azizi-Mazreah and Mohammad T. Manzuri Shalmani and Hamid Barati and Ali Barati", title = "Delay and Energy Consumption Analysis of Conventional SRAM", abstract = "The energy consumption and delay in read/write
operation of conventional SRAM is investigated analytically as well
as by simulation. Explicit analytical expressions for the energy
consumption and delay in read and write operation as a function of
device parameters and supply voltage are derived. The expressions are
useful in predicting the effect of parameter changes on the energy
consumption and speed as well as in optimizing the design of
conventional SRAM. HSPICE simulation in standard 0.25μm CMOS
technology confirms precision of analytical expressions derived from
this paper.", keywords = "Read energy consumption, write energy consumption,read delay, write delay.", volume = "2", number = "1", pages = "106-5", }