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Next Generation Networks and Their Relation with Ad-hoc Networks

Year: 2008 Volume: 2 Issue: 3 882 - 885 Pages

Abstract: The communication networks development and advancement during two last decades has been toward a single goal and that is gradual change from circuit-switched networks to packed switched ones. Today a lot of networks operates are trying to transform the public telephone networks to multipurpose packed switch. This new achievement is generally called "next generation networks". In fact, the next generation networks enable the operators to transfer every kind of services (sound, data and video) on a network. First, in this report the definition, characteristics and next generation networks services and then ad-hoc networks role in the next generation networks are studied.

Delay and Energy Consumption Analysis of Conventional SRAM

Year: 2008 Volume: 2 Issue: 1 106 - 110 Pages

Abstract: The energy consumption and delay in read/write operation of conventional SRAM is investigated analytically as well as by simulation. Explicit analytical expressions for the energy consumption and delay in read and write operation as a function of device parameters and supply voltage are derived. The expressions are useful in predicting the effect of parameter changes on the energy consumption and speed as well as in optimizing the design of conventional SRAM. HSPICE simulation in standard 0.25μm CMOS technology confirms precision of analytical expressions derived from this paper.

A Novel Four-Transistor SRAM Cell with Low Dynamic Power Consumption

Year: 2008 Volume: 2 Issue: 3 437 - 441 Pages

Abstract: This paper presents a novel CMOS four-transistor SRAM cell for very high density and low power embedded SRAM applications as well as for stand-alone SRAM applications. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 20% smaller than a conventional six-transistor cell using same design rules. Also proposed cell uses two word-lines and one pair bit-line. Read operation perform from one side of cell, and write operation perform from another side of cell, and swing voltage reduced on word-lines thus dynamic power during read/write operation reduced. The fabrication process is fully compatible with high-performance CMOS logic technologies, because there is no need to integrate a poly-Si resistor or a TFT load. HSPICE simulation in standard 0.25μm CMOS technology confirms all results obtained from this paper.

A Review of Coverage and Routing for Wireless Sensor Networks

Year: 2008 Volume: 2 Issue: 1 70 - 76 Pages

Abstract: The special constraints of sensor networks impose a number of technical challenges for employing them. In this review, we study the issues and existing protocols in three areas: coverage and routing. We present two types of coverage problems: to determine the minimum number of sensor nodes that need to perform active sensing in order to monitor a certain area; and to decide the quality of service that can be provided by a given sensor network. While most routing protocols in sensor networks are data-centric, there are other types of routing protocols as well, such as hierarchical, location-based, and QoS-aware. We describe and compare several protocols in each group. We present several multipath routing protocols and single-path with local repair routing protocols, which are proposed for recovering from sensor node crashes. We also discuss some transport layer schemes for reliable data transmission in lossy wireless channels.

A Low Power SRAM Base on Novel Word-Line Decoding

Year: 2008 Volume: 2 Issue: 3 651 - 655 Pages

Abstract: This paper proposes a low power SRAM based on five transistor SRAM cell. Proposed SRAM uses novel word-line decoding such that, during read/write operation, only selected cell connected to bit-line whereas, in conventional SRAM (CV-SRAM), all cells in selected row connected to their bit-lines, which in turn develops differential voltages across all bit-lines, and this makes energy consumption on unselected bit-lines. In proposed SRAM memory array divided into two halves and this causes data-line capacitance to reduce. Also proposed SRAM uses one bit-line and thus has lower bit-line leakage compared to CV-SRAM. Furthermore, the proposed SRAM incurs no area overhead, and has comparable read/write performance versus the CV-SRAM. Simulation results in standard 0.25μm CMOS technology shows in worst case proposed SRAM has 80% smaller dynamic energy consumption in each cycle compared to CV-SRAM. Besides, energy consumption in each cycle of proposed SRAM and CV-SRAM investigated analytically, the results of which are in good agreement with the simulation results.