Abstract: In this paper we present two novel 1-bit full adder
cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output
structures are used to design the adder blocks. Characteristic of
dynamic logic leads to higher speeds than the other standard static
full adder cells. Using HSpice and 0.18┬Ám CMOS technology
exhibits a significant decrease in the cell delay which can result in a
considerable reduction in the power-delay product (PDP). The PDP
of Multi-Output design at 1.8v power supply is around 0.15 femto
joule that is 5% lower than conventional dynamic full adder cell and
at least 21% lower than other static full adders.
Abstract: When studying electronics, hands-on experience is considered to be very valuable for a better understanding of the concepts of electricity and electronics. Students lacking sufficient time in the lab are often put at disadvantage. A way to overcome this, is by using interactive multimedia in a virtual environment. Instead of proposing another new ad-hoc simulator for e-learning, we propose in this paper an e-learning platform integrating the SPICE simulator as a web service. This enables to make use of all the functions of the de-facto standard simulator SPICE inelectronics when developing new simulations.
Abstract: In this paper, a new BiCMOS CCII and CCCII,
capable of operate at ±0.5V and having wide dynamic range with
achieved bandwidth of 480MHz and 430MHz respectively have been
proposed. The structures have been found to be insensitive to the
threshold voltage variations. The proposed circuits are suitable for
implementation using 0.25μm BiCMOS technology. Pspice
simulations confirm the performance of the proposed structures.
Abstract: This article presents new current-mode oscillator circuits using CDTAs which is designed from block diagram. The proposed circuits consist of two CDTAs and two grounded capacitors. The condition of oscillation and the frequency of oscillation can be adjusted by electronic method. The circuits have high output impedance and use only grounded capacitors without any external resistor which is very appropriate to future development into an integrated circuit. The results of PSPICE simulation program are corresponding to the theoretical analysis.
Abstract: This paper introduces an adiabatic register file based
on two-phase CPAL (Complementary Pass-Transistor Adiabatic
Logic circuits) with power-gating scheme, which can operate on a
single-phase power clock. A 32×32 single-phase adiabatic register file
with power-gating scheme has been implemented with TSMC 0.18μm
CMOS technology. All the circuits except for the storage cells employ
two-phase CPAL circuits, and the storage cell is based on the
conventional memory one. The two-phase non-overlap power-clock
generator with power-gating scheme is used to supply the proposed
adiabatic register file. Full-custom layouts are drawn. The energy and
functional simulations have been performed using the net-list
extracted from their layouts. Compared with the traditional static
CMOS register file, HSPICE simulations show that the proposed
adiabatic register file can work very well, and it attains about 73%
energy savings at 100 MHz.
Abstract: This paper proposes a synchronized random switching frequency pulse width modulation (SRSFPWM). In this technique, the clock signal is used to control the random noise frequency which is produced by the feedback voltage of a hysteresis circuit. These make the triangular carrier frequency equaling to the random noise frequency in each switching period with the symmetrical positive and negative slopes of triangular carrier. Therefore, there is no error voltage in PWM signal. The PSpice simulated results shown the proposed technique improved the performance in case of low frequency harmonics of PWM signal comparing with conventional random switching frequency PWM.
Abstract: The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been investigated using 0.15um and 0.35um technologies. Compared to the earlier designed 10 transistor full adder, the proposed adder shows a significant improvement in silicon area and power delay product. The whole simulation has been carried out using HSPICE.
Abstract: This paper presented a proposed design for
transcutaneous inductive powering links. The design used to transfer
power and data to the implanted devices such as implanted
Microsystems to stimulate and monitoring the nerves and muscles.
The system operated with low band frequency 13.56 MHZ according
to industrial- scientific – medical (ISM) band to avoid the tissue
heating. For external part, the modulation index is 13 % and the
modulation rate 7.3% with data rate 1 Mbit/s assuming Tbit=1us. The
system has been designed using 0.35-μm fabricated CMOS
technology. The mathematical model is given and the design is
simulated using OrCAD P Spice 16.2 software tool and for real-time
simulation the electronic workbench MULISIM 11 has been used.
The novel circular plane (pancake) coils was simulated using
ANSOFT- HFss software.
Abstract: This paper presents the characterization and design of a capacitive pressure sensor with LC-based 0.35 µm CMOS readout circuit. SPICE is employed to evaluate the characteristics of the readout circuit and COMSOL multiphysics structural analysis is used to simulate the behavior of the pressure sensor. The readout circuit converts the capacitance variation of the pressure sensor into the frequency output. Simulation results show that the proposed pressure sensor has output frequency from 2.50 to 2.28 GHz in a pressure range from 0.1 to 2 MPa almost linearly. The sensitivity of the frequency shift with respect to the applied pressure load is 0.11 GHz/MPa.
Abstract: This paper presents a new general technique for analysis of noise in static log-domain translinear circuits. It is demonstrated that employing this technique, leads to a general, simple and routine method of the noise analysis. The circuit has been simulated by HSPICE. The simulation results are seen to conform to the theoretical analysis and shows benefits of the proposed circuit.
Abstract: This paper presents positive and negative full-wave
rectifier. The proposed structure is based on OTA using
commercially available ICs (LT1228). The features of the proposed
circuit are that: it can rectify and amplify voltage signal with
controllable output magnitude via input bias current: the output
voltage is free from temperature variation. The circuit description
merely consists of 1 single ended and 3 fully differential OTAs. The
performance of the proposed circuit are investigated though PSpice.
They show that the proposed circuit can function as positive/negative
full-wave rectifier, where the voltage input wide-dynamic range from
-5V to 5V. Furthermore, the output voltage is slightly dependent on
the temperature variations.
Abstract: This article presents a current-mode quadrature
oscillator using differential different current conveyor (DDCC) and
voltage differencing transconductance amplifier (VDTA) as active
elements. The proposed circuit is realized fro m a non-inverting
lossless integrator and an inverting second order low-pass filter. The
oscillation condition and oscillation frequency can be
electronically/orthogonally controlled via input bias currents. The
circuit description is very simple, consisting of merely 1 DDCC, 1
VDTA, 1 grounded resistor and 3 grounded capacitors. Using only
grounded elements, the proposed circuit is then suitable for IC
architecture. The proposed oscillator has high output impedance
which is easy to cascade or dive the external load without the buffer
devices. The PSPICE simulation results are depicted, and the given
results agree well with the theoretical anticipation. The power
consumption is approximately 1.76mW at ±1.25V supply voltages.
Abstract: Average current analysis checking the impact of
current flow is very important to guarantee the reliability of
semiconductor systems. As semiconductor process technologies
improve, the coupling capacitance often become bigger than self
capacitances. In this paper, we propose an analytic technique for
analyzing average current on interconnects in multi-conductor
structures. The proposed technique has shown to yield the acceptable
errors compared to HSPICE results while providing computational
efficiency.
Abstract: This article presents a voltage-mode universal
biquadratic filter performing simultaneous 3 standard functions: lowpass,
high-pass and band-pass functions, employing differential
different current conveyor (DDCC) and current controlled current
conveyor (CCCII) as active element. The features of the circuit are
that: the quality factor and pole frequency can be tuned independently
via the input bias currents: the circuit description is very simple,
consisting of 1 DDCC, 2 CCCIIs, 2 electronic resistors and 2
grounded capacitors. Without requiring component matching
conditions, the proposed circuit is very appropriate to further develop
into an integrated circuit. The PSPICE simulation results are
depicted. The given results agree well with the theoretical
anticipation.
Abstract: A current mirror (CM) based on self cascode MOSFETs low voltage analog and mixed mode structures has been proposed. The proposed CM has high output impedance and can operate at 0.5 V. P-Spice simulations confirm the high performance of this CM with a bandwidth of 6.0 GHz at input current of 100 μA.
Abstract: In this paper, a modified CCCII is presented. We have used a current mirror with low supply voltage. This circuit is operated at low supply voltage of ±1V. Tspice simulations for TSMC 0.18μm CMOS Technology has shown that the current and voltage bandwidth are respectively 3.34GHz and 4.37GHz, and parasitic resistance at port X has a value of 169.320 for a control current of 120μA. In order to realize this circuit, we have implemented in this first step a universal current mode filter where the frequency can reach the 134.58MHz. In the second step, we have implemented two simulated inductors: one floating and the other grounded. These two inductors are operated in high frequency and variable depending on bias current I0. Finally, we have used the two last inductors respectively to implement two sinusoidal oscillators domains of frequencies respectively: [470MHz, 692MHz], and [358MHz, 572MHz] for bias currents I0 [80μA, 350μA].
Abstract: Fast delay estimation methods, as opposed to
simulation techniques, are needed for incremental performance
driven layout synthesis. On-chip inductive effects are becoming
predominant in deep submicron interconnects due to increasing clock
speed and circuit complexity. Inductance causes noise in signal
waveforms, which can adversely affect the performance of the circuit
and signal integrity. Several approaches have been put forward which
consider the inductance for on-chip interconnect modelling. But for
even much higher frequency, of the order of few GHz, the shunt
dielectric lossy component has become comparable to that of other
electrical parameters for high speed VLSI design. In order to cope up
with this effect, on-chip interconnect has to be modelled as
distributed RLCG line. Elmore delay based methods, although
efficient, cannot accurately estimate the delay for RLCG interconnect
line. In this paper, an accurate analytical delay model has been
derived, based on first and second moments of RLCG
interconnection lines. The proposed model considers both the effect
of inductance and conductance matrices. We have performed the
simulation in 0.18μm technology node and an error of as low as less
as 5% has been achieved with the proposed model when compared to
SPICE. The importance of the conductance matrices in interconnect
modelling has also been discussed and it is shown that if G is
neglected for interconnect line modelling, then it will result an delay
error of as high as 6% when compared to SPICE.