High Speed NP-CMOS and Multi-Output Dynamic Full Adder Cells
In this paper we present two novel 1-bit full adder
cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output
structures are used to design the adder blocks. Characteristic of
dynamic logic leads to higher speeds than the other standard static
full adder cells. Using HSpice and 0.18┬Ám CMOS technology
exhibits a significant decrease in the cell delay which can result in a
considerable reduction in the power-delay product (PDP). The PDP
of Multi-Output design at 1.8v power supply is around 0.15 femto
joule that is 5% lower than conventional dynamic full adder cell and
at least 21% lower than other static full adders.
[1] J. M. Rabaey, Digital Integrated Circuits, A Design Perspective,
Prentice Hall, Englewood Cliffs, NJ, 1996.
[2] J. Uyemura, CMOS Logic Circuit Design, ISBN 0-7923-8452-0, Kluwer,
1999.
[3] S. M. Kang and Y. Leblebici, CMOS Integrated Circuits, Analysis and
Design, McGraw-Hill, 2003.
[4] S. Issam, A. Khater, A. Bellaouar and M. I. Elmasry, "Circuit techniques
for CMOS low-power high performance multipliers," IEEE J. Solid-
State Circuit, vol. 31, pp. 1535-1544, Oct. 1996.
[5] R. Zimmermann and W. Fichtner, "Low-power logic styles: CMOS
versus pass-transistor logic," IEEE J. Solid-State Circuits, vol. 32, pp.
1079-1090, July 1997.
[6] N. Weste and K. Eshragian, Principles of CMOS VLSI Design: A System
Perspective, Addison-Wesley, 1993.
[7] E. Abu-Shama and M. Bayoumi, "A new cell for low-power adders," in
Proc. Int. Midwest Symp. Circuits Syst., 1995.
[8] N. Zhuang and H. Wu, "A new design of the CMOS full adder," IEEE J.
of Sold-State Circuits, vol. 27, pp. 840-844, May 1992.
[9] K. Navi, O. Kavehie, M. Ruholamini, A. Sahafi, S. Mehrabi and N.
Dadkhahi, "Low-power and high-performance 1-bit CMOS full adder
cell," JCP, Journal of Computers, vol. 3, pp. 48-54, Feb. 2008.
[10] L. Junming, S. Yan, L. Zhenghui and W. Ling, "A novel 10-transistor
low-power high-speed full adder cell," IEEE 6th International
Conference Solid-State and Integrated-Circuit Technology, vol. 2, pp.
1155-1158, Oct. 2001.
[11] A. M. Shams and M. A. Bayoumi, "A structured approach for designing
low-power adders," Proc. 31st Asilomar Conf. Signals, Systems
Computers, vol. 1, pp. 757-761, 1997.
[12] A. M. Shams and M. A. Bayoumi, "A novel high-performance CMOS 1-
bit full-adder cell," IEEE Transactions on Circuits and Systems. II, vol
47, pp. 478-481, May 2000.
[13] A. M. Shams, T. K. Darwish and M. A. Bayoumi, "Performance analysis
of low-power 1-bit CMOS full adder cells," IEEE Transactions on VLSI
Systems, vol. 10, pp. 20-29, Jan. 2002.
[14] A. A. Fayed and M. A. Bayoumi, "A low power 10-transistor full adder
cell for embedded architectures," Proc. IEEE Symp. Circuits and
Systems, vol. 4, pp. 226-229, May 2001, Sydney, Australia.
[15] J. F. Lin, Y. T. Hwang, M. H. Sheu and C. C. Ho, "A novel high-speed
and energy efficient 10-transistor full adder design," IEEE Transactions
on Circuits and Systems I: Regular Papers, vol. 54, pp. 1050-1059,
May 2007.
[16] C. H. Chang, J. Gu and M. Zhang, "A review of 0.18um full adder
performances for tree structure arithmetic circuits," IEEE Trans. Very
Large Scale Integr. (VLSI) Syst., vol. 13, pp. 686-695, Jan. 2005.
[17] M. Sayed and W. Badawy, "Performance analysis of single-bit full adder
cells using 0.18, 0.25 and 0.35um CMOS technologies," IEEE
International Symp. on Circuits and Systems, vol. 3, pp. 559-562, Aug.
2002.
[18] K. Navi, A. Kazeminejad and D. Etiemble, "Performance of CMOS
current mode full adders," IEEE Proc. Int-l. Symposium Multiple Valued
Logic, pp. 27-34, May 1994.
[19] M. Haghparast and K. Navi, "A novel reversible BCD adder for
nanotechnology based systems," American Journal of Applied Sciences
5 (3), ISSN 1546-9239, pp. 282-288, 2008.
[20] K. Navi, O. Kavehie, M. Rouholamini, A. Sahafi and S. Mehrabi, "A
novel CMOS full adder," 20th International Conference on VLSI Design
held jointly with 6th International Conference on Embedded Systems
(VLSID-07), pp. 303-307, Jan. 2007, Bangalore, India.
[1] J. M. Rabaey, Digital Integrated Circuits, A Design Perspective,
Prentice Hall, Englewood Cliffs, NJ, 1996.
[2] J. Uyemura, CMOS Logic Circuit Design, ISBN 0-7923-8452-0, Kluwer,
1999.
[3] S. M. Kang and Y. Leblebici, CMOS Integrated Circuits, Analysis and
Design, McGraw-Hill, 2003.
[4] S. Issam, A. Khater, A. Bellaouar and M. I. Elmasry, "Circuit techniques
for CMOS low-power high performance multipliers," IEEE J. Solid-
State Circuit, vol. 31, pp. 1535-1544, Oct. 1996.
[5] R. Zimmermann and W. Fichtner, "Low-power logic styles: CMOS
versus pass-transistor logic," IEEE J. Solid-State Circuits, vol. 32, pp.
1079-1090, July 1997.
[6] N. Weste and K. Eshragian, Principles of CMOS VLSI Design: A System
Perspective, Addison-Wesley, 1993.
[7] E. Abu-Shama and M. Bayoumi, "A new cell for low-power adders," in
Proc. Int. Midwest Symp. Circuits Syst., 1995.
[8] N. Zhuang and H. Wu, "A new design of the CMOS full adder," IEEE J.
of Sold-State Circuits, vol. 27, pp. 840-844, May 1992.
[9] K. Navi, O. Kavehie, M. Ruholamini, A. Sahafi, S. Mehrabi and N.
Dadkhahi, "Low-power and high-performance 1-bit CMOS full adder
cell," JCP, Journal of Computers, vol. 3, pp. 48-54, Feb. 2008.
[10] L. Junming, S. Yan, L. Zhenghui and W. Ling, "A novel 10-transistor
low-power high-speed full adder cell," IEEE 6th International
Conference Solid-State and Integrated-Circuit Technology, vol. 2, pp.
1155-1158, Oct. 2001.
[11] A. M. Shams and M. A. Bayoumi, "A structured approach for designing
low-power adders," Proc. 31st Asilomar Conf. Signals, Systems
Computers, vol. 1, pp. 757-761, 1997.
[12] A. M. Shams and M. A. Bayoumi, "A novel high-performance CMOS 1-
bit full-adder cell," IEEE Transactions on Circuits and Systems. II, vol
47, pp. 478-481, May 2000.
[13] A. M. Shams, T. K. Darwish and M. A. Bayoumi, "Performance analysis
of low-power 1-bit CMOS full adder cells," IEEE Transactions on VLSI
Systems, vol. 10, pp. 20-29, Jan. 2002.
[14] A. A. Fayed and M. A. Bayoumi, "A low power 10-transistor full adder
cell for embedded architectures," Proc. IEEE Symp. Circuits and
Systems, vol. 4, pp. 226-229, May 2001, Sydney, Australia.
[15] J. F. Lin, Y. T. Hwang, M. H. Sheu and C. C. Ho, "A novel high-speed
and energy efficient 10-transistor full adder design," IEEE Transactions
on Circuits and Systems I: Regular Papers, vol. 54, pp. 1050-1059,
May 2007.
[16] C. H. Chang, J. Gu and M. Zhang, "A review of 0.18um full adder
performances for tree structure arithmetic circuits," IEEE Trans. Very
Large Scale Integr. (VLSI) Syst., vol. 13, pp. 686-695, Jan. 2005.
[17] M. Sayed and W. Badawy, "Performance analysis of single-bit full adder
cells using 0.18, 0.25 and 0.35um CMOS technologies," IEEE
International Symp. on Circuits and Systems, vol. 3, pp. 559-562, Aug.
2002.
[18] K. Navi, A. Kazeminejad and D. Etiemble, "Performance of CMOS
current mode full adders," IEEE Proc. Int-l. Symposium Multiple Valued
Logic, pp. 27-34, May 1994.
[19] M. Haghparast and K. Navi, "A novel reversible BCD adder for
nanotechnology based systems," American Journal of Applied Sciences
5 (3), ISSN 1546-9239, pp. 282-288, 2008.
[20] K. Navi, O. Kavehie, M. Rouholamini, A. Sahafi and S. Mehrabi, "A
novel CMOS full adder," 20th International Conference on VLSI Design
held jointly with 6th International Conference on Embedded Systems
(VLSID-07), pp. 303-307, Jan. 2007, Bangalore, India.
@article{"International Journal of Electrical, Electronic and Communication Sciences:52065", author = "Reza Faghih Mirzaee and Mohammad Hossein Moaiyeri and Keivan Navi", title = "High Speed NP-CMOS and Multi-Output Dynamic Full Adder Cells", abstract = "In this paper we present two novel 1-bit full adder
cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output
structures are used to design the adder blocks. Characteristic of
dynamic logic leads to higher speeds than the other standard static
full adder cells. Using HSpice and 0.18┬Ám CMOS technology
exhibits a significant decrease in the cell delay which can result in a
considerable reduction in the power-delay product (PDP). The PDP
of Multi-Output design at 1.8v power supply is around 0.15 femto
joule that is 5% lower than conventional dynamic full adder cell and
at least 21% lower than other static full adders.", keywords = "Bridge Style, Dynamic Logic, Full Adder, HighSpeed, Multi Output, NP-CMOS, Zipper.", volume = "4", number = "3", pages = "463-7", }
