A high Speed 8 Transistor Full Adder Design Using Novel 3 Transistor XOR Gates
The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been investigated using 0.15um and 0.35um technologies. Compared to the earlier designed 10 transistor full adder, the proposed adder shows a significant improvement in silicon area and power delay product. The whole simulation has been carried out using HSPICE.
[1] M. Hosseinzadeh, S.J. Jassbi, and Keivan Navi, "A Novel Multiple
Valued Logic OHRNS Modulo rn Adder Circuit", International Journal
of Electronics, Circuits and Systems, Vol. 1, No. 4, Fall 2007, pp. 245-
249.
[2] D. Radhakrishnan, "Low-voltage low-power CMOS full adder," in Proc.
IEE Circuits Devices Syst., vol. 148, Feb. 2001, pp. 19-24.
[3] Y. Leblebici, S.M. Kang, CMOS Digital Digital Integrated Circuits,
Singapore: Mc Graw Hill, 2nd edition, 1999, Ch. 7.
[4] J. Wang, S. Fang, and W. Feng, "New efficient designs for XOR and
XNOR functions on the transistor level," IEEE J. Solid-State Circuits,
vol. 29, no. 7, Jul. 1994, pp. 780-786.
[5] H. T. Bui, A. K. Al-Sheraidah, and Y.Wang, "New 4-transistor XOR and
XNOR designs," in Proc. 2nd IEEE Asia Pacific Conf. ASICs, 2000, pp.
25-28.
[6] H.T. Bui, Y. Wang, Y. Jiang , "Design and analysis of 10-transistor full
adders using novel XOR-XNOR gates," in Proc. 5th Int. Conf. Signal
Process., vol. 1, Aug. 21-25, 2000, pp. 619-622.
[7] H. T. Bui, Y. Wang, and Y. Jiang, "Design and analysis of low-power
10-transistor full adders using XOR-XNOR gates," IEEE Trans. Circuits
Syst. II, Analog Digit. Signal Process., vol. 49, no. 1, Jan. 2002, pp. 25-
30.
[8] A. M. Shams, T. K. Darwish, and M. A. Bayoumi, "Performance
analysis of low-power 1-bit CMOS full adder cells," IEEE Trans. Very
Large Scale Integr. (VLSI) Syst., vol. 10, no. 1, Feb. 2002, pp. 20-29.
[9] K.-H. Cheng and C.-S. Huang, "The novel efficient design of
XOR/XNOR function for adder applications," in Proc. IEEE Int. Conf.
Elect., Circuits Syst., vol. 1, Sep. 5-8, 1999, pp. 29-32.
[10] H. Lee and G. E. Sobelman, "New low-voltage circuits for XOR and
XNOR," in Proc. IEEE Southeastcon, Apr. 12-14, 1997, pp. 225-229.
[11] M. Vesterbacka, "A 14-transistor CMOS full adder with full voltage
swing nodes," in Proc. IEEE Worksh. Signal Process. Syst., Oct. 20-22,
1999, pp. 713-722.
[12] G.A. Ruiz, M. Granda, "An area-efficient static CMOS carry-select
adder based on a compact carry look-ahead unit", Microelectronics
Journal, Vol. 35, No. 12, 2004, pp. 939-944.
[13] R. Zimmermann and W. Fichtner, "Low-power logic styles: CMOS
versus pass-transistor logic," IEEE J. Solid-State Circuits, vol. 32, July
1997, pp.1079-90.
[14] N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, A
System Perspective. Reading, MA: Addison-Wesley, 1993.
[15] N. Zhuang and H. Wu, "A new design of the CMOS full adder," IEEE J.
Solid-State Circuits, vol. 27, no. 5, May 1992, pp. 840-844.
[16] E. Abu-Shama and M. Bayoumi, "A new cell for low power adders," in
Proc. Int. Midwest Symp. Circuits Syst., 1995, pp. 1014-1017.
[17] A. M. Shams and M. Bayoumi, "A novel high-performance CMOS 1-bit
full adder cell," IEEE Trans. Circuits Syst. II, Analog Digit. Signal
Process., vol. 47, no. 5, May 2000, pp. 478-481.
[18] R. Shalem, E. John, and L. K. John, "A novel low-power energy
recovery full adder cell," in Proc. Great Lakes Symp. VLSI, Feb. 1999,
pp. 380-383.
[19] A. Fayed and M. Bayoumi, "A low-power 10-transistor full adder cell
for embedded architectures," in Proc. IEEE Symp. Circuits Syst.,
Sydney, Australia, May 2001, pp. 226-229.
[20] J.F. Lin, Y.T.Hwang, M.H. Sheu, C.C. Ho, "A novel high speed and
energy efficient 10 transistor full adder design", IEEE Trans. Circuits
Syst. I, Regular papers, Vol. 54, No.5, May 2007, pp. 1050-1059.
[21] P. Balasubramanian, R.T. Naayagi, "Critical Path Delay and Net Delay
Reduced Tree Structure for Combinational Logic Circuits",
International Journal of Electronics, Circuits and Systems, Vol. 1, No.
1, 2007, pp. 19-29.
[22] Y. Tsividis, Mixed Analog-Digital VLSI Devices and Technology,
Singapore: McGraw Hill, 1st edition, 1996.
[23] M. Morris Mano, Digital Design, Prentice Hall of India, 2nd Edition,
2000.
[24] A. Yurdakul, "Multiplierless implementation of 2D FIR filters",
Integration: The VLSI Journal, Vol. 38, No. 4, 2005, pp. 597-613.
[25] S. Goel, M.A. Elgamel, M.A. Bayoumi, Y. Hanafy, "Design
Methodologies for high performance noise tolerant XOR-XNOR
circuits", IEEE Transactions on Circuits and Systems - I: Regular
Papers, Vol. 53, No. 4, 2006, pp. 867-878.
[1] M. Hosseinzadeh, S.J. Jassbi, and Keivan Navi, "A Novel Multiple
Valued Logic OHRNS Modulo rn Adder Circuit", International Journal
of Electronics, Circuits and Systems, Vol. 1, No. 4, Fall 2007, pp. 245-
249.
[2] D. Radhakrishnan, "Low-voltage low-power CMOS full adder," in Proc.
IEE Circuits Devices Syst., vol. 148, Feb. 2001, pp. 19-24.
[3] Y. Leblebici, S.M. Kang, CMOS Digital Digital Integrated Circuits,
Singapore: Mc Graw Hill, 2nd edition, 1999, Ch. 7.
[4] J. Wang, S. Fang, and W. Feng, "New efficient designs for XOR and
XNOR functions on the transistor level," IEEE J. Solid-State Circuits,
vol. 29, no. 7, Jul. 1994, pp. 780-786.
[5] H. T. Bui, A. K. Al-Sheraidah, and Y.Wang, "New 4-transistor XOR and
XNOR designs," in Proc. 2nd IEEE Asia Pacific Conf. ASICs, 2000, pp.
25-28.
[6] H.T. Bui, Y. Wang, Y. Jiang , "Design and analysis of 10-transistor full
adders using novel XOR-XNOR gates," in Proc. 5th Int. Conf. Signal
Process., vol. 1, Aug. 21-25, 2000, pp. 619-622.
[7] H. T. Bui, Y. Wang, and Y. Jiang, "Design and analysis of low-power
10-transistor full adders using XOR-XNOR gates," IEEE Trans. Circuits
Syst. II, Analog Digit. Signal Process., vol. 49, no. 1, Jan. 2002, pp. 25-
30.
[8] A. M. Shams, T. K. Darwish, and M. A. Bayoumi, "Performance
analysis of low-power 1-bit CMOS full adder cells," IEEE Trans. Very
Large Scale Integr. (VLSI) Syst., vol. 10, no. 1, Feb. 2002, pp. 20-29.
[9] K.-H. Cheng and C.-S. Huang, "The novel efficient design of
XOR/XNOR function for adder applications," in Proc. IEEE Int. Conf.
Elect., Circuits Syst., vol. 1, Sep. 5-8, 1999, pp. 29-32.
[10] H. Lee and G. E. Sobelman, "New low-voltage circuits for XOR and
XNOR," in Proc. IEEE Southeastcon, Apr. 12-14, 1997, pp. 225-229.
[11] M. Vesterbacka, "A 14-transistor CMOS full adder with full voltage
swing nodes," in Proc. IEEE Worksh. Signal Process. Syst., Oct. 20-22,
1999, pp. 713-722.
[12] G.A. Ruiz, M. Granda, "An area-efficient static CMOS carry-select
adder based on a compact carry look-ahead unit", Microelectronics
Journal, Vol. 35, No. 12, 2004, pp. 939-944.
[13] R. Zimmermann and W. Fichtner, "Low-power logic styles: CMOS
versus pass-transistor logic," IEEE J. Solid-State Circuits, vol. 32, July
1997, pp.1079-90.
[14] N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, A
System Perspective. Reading, MA: Addison-Wesley, 1993.
[15] N. Zhuang and H. Wu, "A new design of the CMOS full adder," IEEE J.
Solid-State Circuits, vol. 27, no. 5, May 1992, pp. 840-844.
[16] E. Abu-Shama and M. Bayoumi, "A new cell for low power adders," in
Proc. Int. Midwest Symp. Circuits Syst., 1995, pp. 1014-1017.
[17] A. M. Shams and M. Bayoumi, "A novel high-performance CMOS 1-bit
full adder cell," IEEE Trans. Circuits Syst. II, Analog Digit. Signal
Process., vol. 47, no. 5, May 2000, pp. 478-481.
[18] R. Shalem, E. John, and L. K. John, "A novel low-power energy
recovery full adder cell," in Proc. Great Lakes Symp. VLSI, Feb. 1999,
pp. 380-383.
[19] A. Fayed and M. Bayoumi, "A low-power 10-transistor full adder cell
for embedded architectures," in Proc. IEEE Symp. Circuits Syst.,
Sydney, Australia, May 2001, pp. 226-229.
[20] J.F. Lin, Y.T.Hwang, M.H. Sheu, C.C. Ho, "A novel high speed and
energy efficient 10 transistor full adder design", IEEE Trans. Circuits
Syst. I, Regular papers, Vol. 54, No.5, May 2007, pp. 1050-1059.
[21] P. Balasubramanian, R.T. Naayagi, "Critical Path Delay and Net Delay
Reduced Tree Structure for Combinational Logic Circuits",
International Journal of Electronics, Circuits and Systems, Vol. 1, No.
1, 2007, pp. 19-29.
[22] Y. Tsividis, Mixed Analog-Digital VLSI Devices and Technology,
Singapore: McGraw Hill, 1st edition, 1996.
[23] M. Morris Mano, Digital Design, Prentice Hall of India, 2nd Edition,
2000.
[24] A. Yurdakul, "Multiplierless implementation of 2D FIR filters",
Integration: The VLSI Journal, Vol. 38, No. 4, 2005, pp. 597-613.
[25] S. Goel, M.A. Elgamel, M.A. Bayoumi, Y. Hanafy, "Design
Methodologies for high performance noise tolerant XOR-XNOR
circuits", IEEE Transactions on Circuits and Systems - I: Regular
Papers, Vol. 53, No. 4, 2006, pp. 867-878.
@article{"International Journal of Electrical, Electronic and Communication Sciences:50726", author = "Shubhajit Roy Chowdhury and Aritra Banerjee and Aniruddha Roy and Hiranmay Saha", title = "A high Speed 8 Transistor Full Adder Design Using Novel 3 Transistor XOR Gates", abstract = "The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been investigated using 0.15um and 0.35um technologies. Compared to the earlier designed 10 transistor full adder, the proposed adder shows a significant improvement in silicon area and power delay product. The whole simulation has been carried out using HSPICE.
", keywords = "XOR gate, full adder, improvement in speed, area minimization, transistor count minimization.", volume = "2", number = "10", pages = "2138-7", }
