[1] Jens Sparso, "Principles of Asynchronous Circuit Design: A Systems Perspective,” Kluwer Academic Publishers, 2002
[2] Matthew W. Heath, Wayne P. Burleson, Ian G. Harris, "Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test,” IEEE transactions on Computers, December 2005 (vol. 54 no. 12)
[3] R. W. Apperson, Z. Yu, M. J. Meeuwsen, T. Mohsenin, and B. M. Bass, "A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains,” IEEE Transactions on Very Large Scale Integration, vol. 15, no. 10, pp. 1125–1134, Oct 2007.
[4] Chelcea, T., and Nowick,S.(2004), ‘Robust Interfaces for Mixed Timing Systems’,IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12, 857–873.
[5] Teehan, P., Greenstreet, M., and Lemieux, G. (2007), ‘A Survey and Taxonomy of GALS Design Styles’, IEEE Design and Test of Computers, 24, 418–428.
[6] Chapiro, D.M. (1984), ‘Globally-asynchronous Locally-synchronous Systems’, PhD thesis, Stanford University.
[7] Henkel, J., Wolf, W., and Chakradhar, S. (2004), ‘On-chip Networks: A Scalable, Communication-centric Embedded System Design ‘Proceedings of 17th International Conference VLSI Design, pp. 845–851.
[8] Dally, W.J., and Towles, B. (2001), ‘Route Packets, not Wires: On Chip Interconnection Networks’, in Proceedings of 38th Design Automation Conference, pp. 684–689
[9] Salminen, E., Lahtinen, V., Kuusilinna, K., and Hamalainen, T. (2002), ‘Overview of Bus-based System-on-chip Interconnections’, in Proceedings of IEEE International Symposium on Circuits and Systems, pp. 372–375.
[10] I.E Sutherland, "Micropipelines,” Communications of the ACM, Volume 32 Issue 6, June 1989.
[11] Dasgupta, S., and Yakovlev, A. (2007), ‘Comparative Analysis of GALS Clocking Schemes’, IET Journal of Computers and Digital Techniques, 1, 59–69
[12] W. J. Dally and J. W. Poulton, Digital Systems Engineering.Cambridge, U.K.: Cambridge Univ. Press, 1998.
[13] M. Balch, Complete Digital Design, 1st ed.New York: McGraw-Hill2003.
[14] J. Ebergen, "Squaring the FIFO in GasP,” in Proc. Int. Symp. Asynch.Circuits Syst., 2001, pp. 194–205.
[15] C. E. Molnar, I. W. Jones, W. S. Coates, and J. K. Lexau, "A FIFO ring performance experiment,” in Proc. Int. Symp. Asynch. Circuits Syst.,1997, pp. 279–289.
[16] Xin Wang, TapaniAhonen, JariNurmi, "A Synthesizable RTL Design of Asynchronous FIFO,” Proc. International Symposium on System-on-Chip, 2004.
[17] A.V. Yakovlev, A.M. Koelmans, L.Lavagno, "High-Level Modeling and Design of Asynchronous Interface Logic,” IEEE Design and Test of Computers, Spring 1995.
[18] E. Brunvand, "Low Latency Self-Timed Flow through FIFOs,” in 16th Conference on Advanced Research inVLSI, UC Santa Cruz, March 1995, pp. 76–90.
[19] Chattopadhyay, A., and Zilic, Z. (2005), ‘GALDS: A Complete Framework for Designing Multiclock ASICs and SoCs’, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13, 641–654.
[20] Para Ono, T., and Greenstreet, M. (2009), ‘A Modular Synchronizing FIFO for NoCs’, in Proceedings of 3rd ACM/IEEE International Symposium on Networks-on-Chip, pp. 224–233.
[21] Strano, A., Ludovici, D., and Bertozzi, D. (2010), ‘A Library of Dual-clock FIFOs for Cost-effective and Flexible MPSoC Design’, in Proceedings of International Conference on Embedded Computer Systems (SAMOS), pp. 20–27.
[22] Chakraborty, A., and Greenstreet, M.R. (2003), ‘Efficient Self-timed Interfaces for Crossing Clock Domains’, in Proceedings of 9th International Symposium on Asynchronous Circuits and Systems, pp. 78–88.
[1] Jens Sparso, "Principles of Asynchronous Circuit Design: A Systems Perspective,” Kluwer Academic Publishers, 2002
[2] Matthew W. Heath, Wayne P. Burleson, Ian G. Harris, "Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test,” IEEE transactions on Computers, December 2005 (vol. 54 no. 12)
[3] R. W. Apperson, Z. Yu, M. J. Meeuwsen, T. Mohsenin, and B. M. Bass, "A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains,” IEEE Transactions on Very Large Scale Integration, vol. 15, no. 10, pp. 1125–1134, Oct 2007.
[4] Chelcea, T., and Nowick,S.(2004), ‘Robust Interfaces for Mixed Timing Systems’,IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12, 857–873.
[5] Teehan, P., Greenstreet, M., and Lemieux, G. (2007), ‘A Survey and Taxonomy of GALS Design Styles’, IEEE Design and Test of Computers, 24, 418–428.
[6] Chapiro, D.M. (1984), ‘Globally-asynchronous Locally-synchronous Systems’, PhD thesis, Stanford University.
[7] Henkel, J., Wolf, W., and Chakradhar, S. (2004), ‘On-chip Networks: A Scalable, Communication-centric Embedded System Design ‘Proceedings of 17th International Conference VLSI Design, pp. 845–851.
[8] Dally, W.J., and Towles, B. (2001), ‘Route Packets, not Wires: On Chip Interconnection Networks’, in Proceedings of 38th Design Automation Conference, pp. 684–689
[9] Salminen, E., Lahtinen, V., Kuusilinna, K., and Hamalainen, T. (2002), ‘Overview of Bus-based System-on-chip Interconnections’, in Proceedings of IEEE International Symposium on Circuits and Systems, pp. 372–375.
[10] I.E Sutherland, "Micropipelines,” Communications of the ACM, Volume 32 Issue 6, June 1989.
[11] Dasgupta, S., and Yakovlev, A. (2007), ‘Comparative Analysis of GALS Clocking Schemes’, IET Journal of Computers and Digital Techniques, 1, 59–69
[12] W. J. Dally and J. W. Poulton, Digital Systems Engineering.Cambridge, U.K.: Cambridge Univ. Press, 1998.
[13] M. Balch, Complete Digital Design, 1st ed.New York: McGraw-Hill2003.
[14] J. Ebergen, "Squaring the FIFO in GasP,” in Proc. Int. Symp. Asynch.Circuits Syst., 2001, pp. 194–205.
[15] C. E. Molnar, I. W. Jones, W. S. Coates, and J. K. Lexau, "A FIFO ring performance experiment,” in Proc. Int. Symp. Asynch. Circuits Syst.,1997, pp. 279–289.
[16] Xin Wang, TapaniAhonen, JariNurmi, "A Synthesizable RTL Design of Asynchronous FIFO,” Proc. International Symposium on System-on-Chip, 2004.
[17] A.V. Yakovlev, A.M. Koelmans, L.Lavagno, "High-Level Modeling and Design of Asynchronous Interface Logic,” IEEE Design and Test of Computers, Spring 1995.
[18] E. Brunvand, "Low Latency Self-Timed Flow through FIFOs,” in 16th Conference on Advanced Research inVLSI, UC Santa Cruz, March 1995, pp. 76–90.
[19] Chattopadhyay, A., and Zilic, Z. (2005), ‘GALDS: A Complete Framework for Designing Multiclock ASICs and SoCs’, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13, 641–654.
[20] Para Ono, T., and Greenstreet, M. (2009), ‘A Modular Synchronizing FIFO for NoCs’, in Proceedings of 3rd ACM/IEEE International Symposium on Networks-on-Chip, pp. 224–233.
[21] Strano, A., Ludovici, D., and Bertozzi, D. (2010), ‘A Library of Dual-clock FIFOs for Cost-effective and Flexible MPSoC Design’, in Proceedings of International Conference on Embedded Computer Systems (SAMOS), pp. 20–27.
[22] Chakraborty, A., and Greenstreet, M.R. (2003), ‘Efficient Self-timed Interfaces for Crossing Clock Domains’, in Proceedings of 9th International Symposium on Asynchronous Circuits and Systems, pp. 78–88.