Abstract: There are multiple ways to implement a decimator
filter. This paper addresses usage of CIC (cascaded-integrator-comb)
filter and HB (half band) filter as the decimator filter to reduce the
frequency sample rate by factor of 64 and detail of the
implementation step to realize this design in hardware. Low power
design approach for CIC filter and half band filter will be discussed.
The filter design is implemented through MATLAB system
modeling, ASIC (application specific integrated circuit) design flow
and verified using a FPGA (field programmable gate array) board
and MATLAB analysis.
Abstract: Developments in communication technologies
especially in wireless have enabled the progress of low-cost and lowpower
wireless sensor networks (WSNs). The features of such WSN
are holding minimal energy, weak computational capabilities,
wireless communication and an open-medium nature where sensors
are deployed. WSN is underpinned by application driven such as
military applications, the health sector, etc. Due to the intrinsic nature
of the network and application scenario, WSNs are vulnerable to
many attacks externally and internally. In this paper we have focused
on the types of internal attacks of WSNs based on OSI model and
discussed some security requirements, characterizers and challenges
of WSNs, by which to contribute to the WSN-s security research.
Abstract: In this paper, based on a novel synthesis, a set of new simplified circuit design to implement the linguistic-hedge operations for adjusting the fuzzy membership function set is presented. The circuits work in current-mode and employ floating-gate MOS (FGMOS) transistors that operate in weak inversion region. Compared to the other proposed circuits, these circuits feature severe reduction of the elements number, low supply voltage (0.7V), low power consumption (60dB). In this paper, a set of fuzzy linguistic hedge circuits, including absolutely, very, much more, more, plus minus, more or less and slightly, has been implemented in 0.18 mm CMOS process. Simulation results by Hspice confirm the validity of the proposed design technique and show high performance of the circuits.
Abstract: A new power regulator controller with multiple-access
PID compensator is proposed, which can achieve a minimum memory
requirement for fully table look-up. The proposed regulator controller
employs hysteresis comparators, an error process unit (EPU) for
voltage regulation, a multiple-access PID compensator and a lowpower-
consumption digital PWM (DPWM). Based on the multipleaccess
mechanism, the proposed controller can alleviate the penalty of
large amount of memory employed for fully table look-up based PID
compensator in the applications of power regulation. The proposed
controller has been validated with simulation results.