Abstract: This paper presents a silicon controller rectifier (SCR)
based ESD protection circuit for IC. The proposed ESD protection
circuit has low trigger voltage and high holding voltage compared with
conventional SCR ESD protection circuit. Electrical characteristics of
the proposed ESD protection circuit are simulated and analyzed using
TCAD simulator. The proposed ESD protection circuit verified
effective low voltage ESD characteristics with low trigger voltage and
high holding voltage.
Abstract: In this paper a novel high output impedance, low input impedance, wide bandwidth, very simple current mirror with input and output voltage requirements less than that of a simple current mirror is presented. These features are achieved with very simple structure avoiding extra large node impedances to ensure high bandwidth operation. The circuit's principle of operation is discussed and compared to simple and low voltage cascode (LVC) current mirrors. Such outstanding features of this current mirror as high output impedance ~384K, low input impedance~6.4, wide bandwidth~178MHz, low input voltage ~ 362mV, low output voltage ~ 38mV and low current transfer error ~4% (all at 50μA) makes it an outstanding choice for high performance applications. Simulation results in BSIM 0.35μm CMOS technology with HSPICE are given in comparison with simple, and LVC current mirrors to verify and validate the performance of the proposed current mirror.
Abstract: Three similar negative differential resistance (NDR)
profiles with both high peak to valley current density ratio (PVCDR)
value and high peak current density (PCD) value in unity resonant
tunneling electronic circuit (RTEC) element is developed in this paper.
The PCD values and valley current density (VCD) values of the three
NDR curves are all about 3.5 A and 0.8 A, respectively. All PV values
of NDR curves are 0.40 V, 0.82 V, and 1.35 V, respectively. The VV
values are 0.61 V, 1.07 V, and 1.69 V, respectively. All PVCDR
values reach about 4.4 in three NDR curves. The PCD value of 3.5 A
in triple PVCDR RTEC element is better than other resonant
tunneling devices (RTD) elements. The high PVCDR value is
concluded the lower VCD value about 0.8 A. The low VCD value is
achieved by suitable selection of resistors in triple PVCDR RTEC
element. The low PV value less than 1.35 V possesses low power
dispersion in triple PVCDR RTEC element. The designed multiple
value logical level (MVLL) system using triple PVCDR RTEC
element provides equidistant logical level. The logical levels of
MVLL system are about 0.2 V, 0.8 V, 1.5 V, and 2.2 V from low
voltage to high voltage and then 2.2 V, 1.3 V, 0.8 V, and 0.2 V from
high voltage back to low voltage in half cycle of sinusoid wave. The
output level of four levels MVLL system is represented in 0.3 V, 1.1 V,
1.7 V, and 2.6 V, which satisfies the NMP condition of traditional
two-bit system. The remarkable logical characteristic of improved
MVLL system with paralleled capacitor are with four significant
stable logical levels about 220 mV, 223 mV, 228 mV, and 230 mV.
The stability and articulation of logical levels of improved MVLL
system are outstanding. The average holding time of improved MVLL
system is approximately 0.14 μs. The holding time of improved
MVLL system is fourfold than of basic MVLL system. The function of
additional capacitor in the improved MVLL system is successfully
discovered.
Abstract: This paper presents two prototypes of low power low voltage current mode 9 bit pipelined a/d converters. The first and the second converters are configured of 1.5 bit and 2.5 bit stages, respectively. The a/d converter structures are composed of current mode building blocks and final comparator block which converts the analog current signal into digital voltage signal. All building blocks have been designed in CMOS AMS 0.35μm technology, then simulated to verify proposed concept. The performances of both converters are compared to performances of known current mode and voltage mode switched capacitance converter structures. Low power consumption and small chip area are advantages of the proposed converters.
Abstract: The source voltage of high-power fuel cell shows strong load dependence at comparatively low voltage levels. In order to provide the voltage of 750V on the DC-link for feeding electrical energy into the mains via a three phase inverter a step-up converter with a large step-up ratio is required. The output voltage of this DC/DC-converter must be stabile during variations of the load current and the voltage of the fuel cell. This paper presents the methods and results of the calculation of the efficiency and the expense for the realization for the circuits of the DC/DC-converter that meet these requirements.
Abstract: This paper presents a low-voltage low-power differential linear transconductor with near rail-to-rail input swing. Based on the current-mirror OTA topology, the proposed transconductor combines the Flipped Voltage Follower (FVF) technique to linearize the transconductor behavior that leads to class- AB linear operation and the virtual transistor technique to lower the effective threshold voltages of the transistors which offers an advantage in terms of low supply requirement. Design of the OTA has been discussed. It operates at supply voltages of about ±0.8V. Simulation results for 0.18μm TSMC CMOS technology show a good input range of 1Vpp with a high DC gain of 81.53dB and a total harmonic distortion of -40dB at 1MHz for an input of 1Vpp. The main aim of this paper is to present and compare new OTA design with high transconductance, which has a potential to be used in low voltage applications.
Abstract: This study examines the design and construction of AC Electronics load surge protection in order to carry electric surge load arisen from faults in low voltage electricity system (single phase/220V) by using the principle of electronics load clamping voltage during induction period so that electric voltage could go through to safe load and continue to work. The qualification of the designed device could prevent both transient over voltage and voltage swell. Both will work in cooperation, resulting in the ability to improve and modify the quality of electrical power in Thailand electricity distribution system more effective than the past and help increase the lifetime of electric appliances, electric devices, and electricity protection equipments.
Abstract: Multiplication algorithms have considerable effect on
processors performance. A new high-speed, low-power
multiplication algorithm has been presented using modified Dadda
tree structure. Three important modifications have been implemented
in inner product generation step, inner product reduction step and
final addition step. Optimized algorithms have to be used into basic
computation components, such as multiplication algorithms. In this
paper, we proposed a new algorithm to reduce power, delay, and
transistor count of a multiplication algorithm implemented using low
power modified counter. This work presents a novel design for
Dadda multiplication algorithms. The proposed multiplication
algorithm includes structured parts, which have important effect on
inner product reduction tree. In this paper, a 1.3V, 64-bit carry hybrid
adder is presented for fast, low voltage applications. The new 64-bit
adder uses a new circuit to implement the proposed carry hybrid
adder. The new adder using 80 nm CMOS technology has been
implemented on 700 MHz clock frequency. The proposed
multiplication algorithm has achieved 14 percent improvement in
transistor count, 13 percent reduction in delay and 12 percent
modification in power consumption in compared with conventional
designs.
Abstract: Multiphasing of dc-dc converters has been known to give technical and economical benefits to low voltage high power buck regulator modules. A major advantage of multiphasing dc-dc converters is the improvement of input and output performances in the buck converter. From this aspect, a potential use would be in renewable energy where power quality plays an important factor. This paper presents the design of a 2-phase 200W boost converter for battery charging application. Analysis of results from hardware measurement of the boost converter demonstrates the benefits of using multiphase. Results from the hardware prototype of the 2-phase boost converter further show the potential extension of multiphase beyond its commonly used low voltage high current domains.
Abstract: In this paper, we implement a modern serial backplane
platform for telecommunication inter-rack systems. For combination
high reliability and low cost protocol property, we applied high level
data link control (HDLC) protocol with low voltage differential
signaling (LVDS) bus for card to card communicated over backplane.
HDLC protocol is a high performance with several operation modes
and is famous in telecommunication systems. LVDS bus is a high
reliability with high immunity against electromagnetic interference
(EMI) and noise.
Abstract: In this paper we promote the Ultra Low Voltage (ULV) NAND gate to replace either partly or entirely the encryption block of a design to withstand power analysis attack.
Abstract: A new low-voltage floating gate MOSFET (FGMOS)
based squarer using square law characteristic of the FGMOS is
proposed in this paper. The major advantages of the squarer are simplicity,
rail-to-rail input dynamic range, low total harmonic distortion,
and low power consumption. The proposed circuit is biased without
body effect. The circuit is designed and simulated using SPICE in
0.25μm CMOS technology. The squarer is operated at the supply
voltages of ±0.75V . The total harmonic distortion (THD) for the
input signal 0.75Vpp at 25 KHz, and maximum power consumption
were found to be less than 1% and 319μW respectively.
Abstract: This paper describes a three-dimensional thermal
model of the current path included in the low voltage power circuit
breakers. The model can be used to analyse the thermal behaviour of
the current path during both steady-state and transient conditions.
The current path lengthwise temperature distribution and timecurrent
characteristic of the terminal connections of the power circuit
breaker have been obtained. The influence of the electric current and
voltage drop on main electric contact of the circuit breaker has been
investigated. To validate the three-dimensional thermal model, some
experimental tests have been done. There is a good correlation
between experimental and simulation results.
Abstract: Ovshinsky initiated scientific research in the field of
amorphous and disordered materials that continues to this day. The
Ovshinsky Effect where the resistance of thin GST films is
significantly reduced upon the application of low voltage is of
fundamental importance in phase-change - random access memory
(PC-RAM) devices.GST stands for GdSbTe chalcogenide type
glasses.However, the Ovshinsky Effect is not without controversy.
Ovshinsky thought the resistance of GST films is reduced by the
redistribution of charge carriers; whereas, others at that time including
many PC-RAM researchers today argue that the GST resistance
changes because the GST amorphous state is transformed to the
crystalline state by melting, the heat supplied by external heaters. In
this controversy, quantum mechanics (QM) asserts the heat capacity of
GST films vanishes, and therefore melting cannot occur as the heat
supplied cannot be conserved by an increase in GST film
temperature.By precluding melting, QM re-opens the controversy
between the melting and charge carrier mechanisms. Supporting
analysis is presented to show that instead of increasing GST film
temperature, conservation proceeds by the QED induced creation of
photons within the GST film, the QED photons confined by TIR. QED
stands for quantum electrodynamics and TIR for total internal
reflection. The TIR confinement of QED photons is enhanced by the
fact the absorbedheat energy absorbed in the GST film is concentrated
in the TIR mode because of their high surface to volume ratio. The
QED photons having Planck energy beyond the ultraviolet produce
excitons by the photoelectric effect, the electrons and holes of which
reduce the GST film resistance.
Abstract: Resistive switching of aluminum nitride (AlNx) thin film was demonstrated in a TaN/AlNx/TiN memory cell that was prepared by sputter deposition techniques. The memory cell showed bipolar switching of resistance between +3.5 V and –3.5 V. The resistance ratio of high resistance state (HRS) to low resistance state (HRS), RHRS/RLRS, was about 2 over 100 cycles of endurance test. Both the LRS and HRS of the memory cell exhibited ohmic conduction at low voltages and Poole-Frenkel emission at high voltages. The electrical conduction in the TaN/AlNx/TiN memory cell was possibly attributed to the interactions between charges and defects in the AlNx film.
Abstract: Power transformer consists of components which are
under consistent thermal and electrical stresses. The major
component which degrades under these stresses is the paper
insulation of the power transformer. At site, lightning impulses and
cable faults may cause the winding deformation. In addition, the
winding may deform due to impact during transportation. A
deformed winding will excite more stress to its insulating paper thus
will degrade it. Insulation degradation will shorten the life-span of
the transformer. Currently there are two methods of detecting the
winding deformation which are Sweep Frequency Response
Analysis (SFRA) and Low Voltage Impulse Test (LVI). The latter
injects current pulses to the winding and capture the admittance
plot. In this paper, a transformer which experienced overheating and
arcing was identified, and both SFRA and LVI were performed.
Next, the transformer was brought to the factory for untanking. The
untanking results revealed that the LVI is more accurate than the
SFRA method for this case study.
Abstract: This paper study the segmented split capacitor
Digital-to-Analog Converter (DAC) implemented in a differentialtype
12-bit Successive Approximation Analog-to-Digital Converter
(SA-ADC). The series capacitance split array method employed as it
reduced the total area of the capacitors required for high resolution
DACs. A 12-bit regular binary array structure requires 2049 unit
capacitors (Cs) while the split array needs 127 unit Cs. These results
in the reduction of the total capacitance and power consumption of
the series split array architectures as to regular binary-weighted
structures. The paper will show the 12-bit DAC series split capacitor
with 4-bit thermometer coded DAC architectures as well as the
simulation and measured results.
Abstract: In this paper, a new efficient method for load balancing in low voltage distribution systems is presented. The proposed method introduces an improved Leap-frog method for optimization. The proposed objective function includes the difference between three phase currents, as well as two other terms to provide the integer property of the variables; where the latter are the status of the connection of loads to different phases. Afterwards, a new algorithm is supplemented to undertake the integer values for the load connection status. Finally, the method is applied to different parts of Tabriz low voltage network, where the results have shown the good performance of the proposed method.
Abstract: The system is made with main distributed components:
First Level: Industrial Computers placed in Control Room (monitors thermal and electrical processes based on the data provided by the second level); Second Level: PLCs which collects data from process and transmits information on the first level; also takes commands from this level which are further, passed to execution elements from third
level; Third Level: field elements consisting in 3 categories: data collecting elements; data transfer elements from the third level to the second; execution elements which take commands from the second
level PLCs and executes them after which transmits the confirmation of execution to them. The purpose of the automatic functioning is the optimization of the co-generative electrical energy commissioning in the national
energy system and the commissioning of thermal energy to the consumers.
The integrated system treats the functioning of all the equipments and devices as a whole: Gas Turbine Units (GTU); MT 20kV Medium Voltage Station (MVS); 0,4 kV Low Voltage Station (LVS); Main Hot Water Boilers (MHW); Auxiliary Hot Water Boilers (AHW); Gas Compressor Unit (GCU); Thermal Agent Circulation
Pumping Unit (TPU); Water Treating Station (WTS).
Abstract: Since the 80s huge efforts have been made to utilize
renewable energy sources to generate electric power. This paper
reports some aspects of integration of the distributed generators into
the low voltage distribution networks. An assessment of impact of the
distributed generators on the reliability indices of low voltage
network is performed. Results obtained from case study using low
voltage network, are presented and discussed.