Abstract: This paper presents the development of a single-ended 38.5 kS/s 10-bit programmable reference SAR ADC which is realized in MIMOS’s 0.35 µm CMOS process. The design uses a resistive DAC, a dynamic comparator with pre-amplifier and a SAR digital logic to create 10 effective bits ADC. A programmable reference circuitry allows the ADC to operate with different input range from 0.6 V to 2.1 V. The ADC consumed less than 7.5 mW power with a 3 V supply.
Abstract: This paper presents the development of a 38.5 kS/s 10-bit low power SAR ADC which is realized in MIMOS’s 0.35 µm CMOS process. The design uses a resistive DAC, a dynamic comparator with pre-amplifier and SAR digital logic to create 10 effective bits while consuming less than 7.8 mW with a 3.3 V power supply.
Abstract: This paper study the segmented split capacitor
Digital-to-Analog Converter (DAC) implemented in a differentialtype
12-bit Successive Approximation Analog-to-Digital Converter
(SA-ADC). The series capacitance split array method employed as it
reduced the total area of the capacitors required for high resolution
DACs. A 12-bit regular binary array structure requires 2049 unit
capacitors (Cs) while the split array needs 127 unit Cs. These results
in the reduction of the total capacitance and power consumption of
the series split array architectures as to regular binary-weighted
structures. The paper will show the 12-bit DAC series split capacitor
with 4-bit thermometer coded DAC architectures as well as the
simulation and measured results.