High-Resolution 12-Bit Segmented Capacitor DAC in Successive Approximation ADC
This paper study the segmented split capacitor
Digital-to-Analog Converter (DAC) implemented in a differentialtype
12-bit Successive Approximation Analog-to-Digital Converter
(SA-ADC). The series capacitance split array method employed as it
reduced the total area of the capacitors required for high resolution
DACs. A 12-bit regular binary array structure requires 2049 unit
capacitors (Cs) while the split array needs 127 unit Cs. These results
in the reduction of the total capacitance and power consumption of
the series split array architectures as to regular binary-weighted
structures. The paper will show the 12-bit DAC series split capacitor
with 4-bit thermometer coded DAC architectures as well as the
simulation and measured results.
[1] S. Long, J. Wu, X. Xia, L, Shi, A1.8V 3.1mW
SuccessiveApproximation ADC in Systemon-Chip, Springer Science
+Business Media, LLC 2008.
[2] A. Basu, V. Lee, A. Ma, A 10-bit 10MS/sSuccessive Approximation
A/D Converter in0.35um CMOS, University of Michigan, 2002.H. Poor,
An Introduction to Signal Detection and Estimation. New York:
Springer-Verlag, 1985, ch. 4.
[3] D. Draxelmayr, "A 6b 600MHz 10mW ADC Array in Digital 90nm
CMOS," ISSCCDig. Tech. Papers, pp. 264-265, Feb. 2004.
[4] N. Verma and A. Chandrakasan, "An Ultra Low Energy 12-bit Rate-
Resolution ScalableSAR ADC for Wireless Sensor Nodes," IEEE J.
Solid-State Circuits, vol. 42, no. 6, pp.1196--1205, Jun. 2007.
[5] R. J. Baker, H. W. Li, and D. E. Boyce, CMOS Circuit Design, Layout
and Simulation.New York: IEEE Press, 1998.
[6] Ji-Yong Um, Digital-domain calibration of split-capacitor DAC with no
extra calibration DAC for a differential-type SAR ADCSolid State
Circuits Conference (A-SSCC), 2011 IEEE Asian.
[7] Ikeda Y, A 14-bit 100-MS/s digitally calibrated binary-weighted currentsteering
CMOS DAC without calibration ADC, Solid-State Circuits
Conference, 2007. ASSCC '07. IEEE Asian.
[8] YanfeiChen, Split capacitor DAC mismatch calibration in successive
approximation ADC, Custom Integrated Circuits Conference, 2009.
CICC '09. IEEE.
[1] S. Long, J. Wu, X. Xia, L, Shi, A1.8V 3.1mW
SuccessiveApproximation ADC in Systemon-Chip, Springer Science
+Business Media, LLC 2008.
[2] A. Basu, V. Lee, A. Ma, A 10-bit 10MS/sSuccessive Approximation
A/D Converter in0.35um CMOS, University of Michigan, 2002.H. Poor,
An Introduction to Signal Detection and Estimation. New York:
Springer-Verlag, 1985, ch. 4.
[3] D. Draxelmayr, "A 6b 600MHz 10mW ADC Array in Digital 90nm
CMOS," ISSCCDig. Tech. Papers, pp. 264-265, Feb. 2004.
[4] N. Verma and A. Chandrakasan, "An Ultra Low Energy 12-bit Rate-
Resolution ScalableSAR ADC for Wireless Sensor Nodes," IEEE J.
Solid-State Circuits, vol. 42, no. 6, pp.1196--1205, Jun. 2007.
[5] R. J. Baker, H. W. Li, and D. E. Boyce, CMOS Circuit Design, Layout
and Simulation.New York: IEEE Press, 1998.
[6] Ji-Yong Um, Digital-domain calibration of split-capacitor DAC with no
extra calibration DAC for a differential-type SAR ADCSolid State
Circuits Conference (A-SSCC), 2011 IEEE Asian.
[7] Ikeda Y, A 14-bit 100-MS/s digitally calibrated binary-weighted currentsteering
CMOS DAC without calibration ADC, Solid-State Circuits
Conference, 2007. ASSCC '07. IEEE Asian.
[8] YanfeiChen, Split capacitor DAC mismatch calibration in successive
approximation ADC, Custom Integrated Circuits Conference, 2009.
CICC '09. IEEE.
@article{"International Journal of Electrical, Electronic and Communication Sciences:54729", author = "Wee Leong Son and Hasmayadi Abdul Majid and Rohana Musa", title = "High-Resolution 12-Bit Segmented Capacitor DAC in Successive Approximation ADC", abstract = "This paper study the segmented split capacitor
Digital-to-Analog Converter (DAC) implemented in a differentialtype
12-bit Successive Approximation Analog-to-Digital Converter
(SA-ADC). The series capacitance split array method employed as it
reduced the total area of the capacitors required for high resolution
DACs. A 12-bit regular binary array structure requires 2049 unit
capacitors (Cs) while the split array needs 127 unit Cs. These results
in the reduction of the total capacitance and power consumption of
the series split array architectures as to regular binary-weighted
structures. The paper will show the 12-bit DAC series split capacitor
with 4-bit thermometer coded DAC architectures as well as the
simulation and measured results.", keywords = "Successive Approximation Register Analog-to-
Digital Converter, SAR ADC, Low voltage ADC.", volume = "6", number = "12", pages = "1441-4", }