Abstract: In traditional dyeing of natural fibers with natural dyes, metal salts are commonly used to increase color stability. This method always carries the risk of environmental pollution (contamination of arable soils and fresh groundwater) due to the release of dyeing effluents containing large amounts of metal. Therefore, researchers are always looking for new methods to obtain a green dyeing system. In this research, the use of the enzymatic dyeing method to prevent environmental pollution with metals and reduce production costs has been proposed. After degumming and bleaching, raw silk fabrics were dyed with natural dyes (Madder and Sumac) by three methods (pre-mordanting with a metal salt, one-step enzymatic dyeing, and two-step enzymatic dyeing). Results show that silk dyed with natural dyes by the enzymatic method has higher color strength and colorfastness than the pretreated with a metal salt. Also, the amount of remained dyes in the dyeing wastewater is significantly reduced by the enzymatic method. It is found that the enzymatic dyeing method leads to improvement of dye absorption, color strength, soft hand, no change in color shade, low production costs (due to low dyeing temperature), and a significant reduction in environmental pollution.
Abstract: Chain Ladder (CL) method, Expected Loss Ratio (ELR) method and Bornhuetter-Ferguson (BF) method, in addition to more complex transition-rate modeling, are commonly used actuarial reserving methods in general insurance. There is limited published research about their relative performance in the context of Mortgage Insurance (MI). In our experience, these traditional techniques pose unique challenges and do not provide stable claim estimates for medium to longer term liabilities. The relative strengths and weaknesses among various alternative approaches revolve around: stability in the recent loss development pattern, sufficiency and reliability of loss development data, and agreement/disagreement between reported losses to date and ultimate loss estimate. CL method results in volatile reserve estimates, especially for accident periods with little development experience. The ELR method breaks down especially when ultimate loss ratios are not stable and predictable. While the BF method provides a good tradeoff between the loss development approach (CL) and ELR, the approach generates claim development and ultimate reserves that are disconnected from the ever-to-date (ETD) development experience for some accident years that have more development experience. Further, BF is based on subjective a priori assumption. The fundamental shortcoming of these methods is their inability to model exogenous factors, like the economy, which impact various cohorts at the same chronological time but at staggered points along their life-time development. This paper proposes an alternative approach of parametrizing the loss development curve and using logistic regression to generate the ultimate loss estimate for each homogeneous group (accident year or delinquency period). The methodology was tested on an actual MI claim development dataset where various cohorts followed a sigmoidal trend, but levels varied substantially depending upon the economic and operational conditions during the development period spanning over many years. The proposed approach provides the ability to indirectly incorporate such exogenous factors and produce more stable loss forecasts for reserving purposes as compared to the traditional CL and BF methods.
Abstract: The application of combustion technologies for thermal conversion of biomass and solid wastes to energy has been a major solution to the effective handling of wastes over a long period of time. Lab-scale biomass combustion systems have been observed to be economically viable and socially acceptable, but major concerns are the environmental impacts of the process and deviation of temperature distribution within the combustion chamber. Both high and low combustion chamber temperature may affect the overall combustion efficiency and gaseous emissions. Therefore, there is an urgent need to develop a control system which measures the deviations of chamber temperature from set target values, sends these deviations (which generates disturbances in the system) in the form of feedback signal (as input), and control operating conditions for correcting the errors. In this research study, major components of the feedback control system were determined, assembled, and tested. In addition, control algorithms were developed to actuate operating conditions (e.g., air velocity, fuel feeding rate) using ladder logic functions embedded in the Programmable Logic Controller (PLC). The developed control algorithm having chamber temperature as a feedback signal is integrated into the lab-scale swirling fluidized bed combustor (SFBC) to investigate the temperature distribution at different heights of the combustion chamber based on various operating conditions. The air blower rates and the fuel feeding rates obtained from automatic control operations were correlated with manual inputs. There was no observable difference in the correlated results, thus indicating that the written PLC program functions were adequate in designing the experimental study of the lab-scale SFBC. The experimental results were analyzed to study the effect of air velocity operating at 222-273 ft/min and fuel feeding rate of 60-90 rpm on the chamber temperature. The developed temperature-based feedback control system was shown to be adequate in controlling the airflow and the fuel feeding rate for the overall biomass combustion process as it helps to minimize the steady-state error.
Abstract: Autonomous driving systems require high reliability to provide people with a safe and comfortable driving experience. However, despite the development of a number of vehicle sensors, it is difficult to always provide high perceived performance in driving environments that vary from time to season. The image segmentation method using deep learning, which has recently evolved rapidly, provides high recognition performance in various road environments stably. However, since the system controls a vehicle in real time, a highly complex deep learning network cannot be used due to time and memory constraints. Moreover, efficient networks are optimized for GPU environments, which degrade performance in embedded processor environments equipped simple hardware accelerators. In this paper, a semantic segmentation network, matrix multiplication accelerator network (MMANet), optimized for matrix multiplication accelerator (MMA) on Texas instrument digital signal processors (TI DSP) is proposed to improve the recognition performance of autonomous driving system. The proposed method is designed to maximize the number of layers that can be performed in a limited time to provide reliable driving environment information in real time. First, the number of channels in the activation map is fixed to fit the structure of MMA. By increasing the number of parallel branches, the lack of information caused by fixing the number of channels is resolved. Second, an efficient convolution is selected depending on the size of the activation. Since MMA is a fixed, it may be more efficient for normal convolution than depthwise separable convolution depending on memory access overhead. Thus, a convolution type is decided according to output stride to increase network depth. In addition, memory access time is minimized by processing operations only in L3 cache. Lastly, reliable contexts are extracted using the extended atrous spatial pyramid pooling (ASPP). The suggested method gets stable features from an extended path by increasing the kernel size and accessing consecutive data. In addition, it consists of two ASPPs to obtain high quality contexts using the restored shape without global average pooling paths since the layer uses MMA as a simple adder. To verify the proposed method, an experiment is conducted using perfsim, a timing simulator, and the Cityscapes validation sets. The proposed network can process an image with 640 x 480 resolution for 6.67 ms, so six cameras can be used to identify the surroundings of the vehicle as 20 frame per second (FPS). In addition, it achieves 73.1% mean intersection over union (mIoU) which is the highest recognition rate among embedded networks on the Cityscapes validation set.
Abstract: Egypt has countless prestigious buildings and diversity of cultural heritage which are located in many cities. Most of the researchers, archaeologists, stakeholders and governmental bodies are paying more attention to the big cities such as Cairo and Alexandria, due to the country’s centralization nature. However, there are other historic cities that are grossly neglected and in need of emergency conservation. For instance, Port Said which is a former colonial city that was established in nineteenth century located at the edge of the northeast Egyptian coast between the Mediterranean Sea and the Suez Canal. This city is chosen because it presents one of the important Egyptian archaeological sites that archive Egyptian architecture of the 19th and 20th centuries. The historic urban fabric is divided into three main districts; the Arab, the European (Al-Afrang), and Port Fouad. The European district is selected to be the research case study as it has culture diversity, significant buildings, and includes the largest number of the listed heritage buildings in Port Said. Based on questionnaires and interviews, since 2003 several initiative trials have been taken by Alliance Francaise, the National Organization for Urban Harmony (NOUH), some Non-Governmental Organizations (NGOs), and few number of community residents to highlight the important city legacy and protect it from being demolished. Unfortunately, the limitation of their participation in decision-making policies is considered a crucial threat facing sustainable heritage conservation. Therefore, encouraging the local community to participate in their architecture heritage conservation would create a self-confident one, capable of making decisions for the city’s future development. This paper aims to investigate the role of the local inhabitants in protecting their buildings heritage through listing the community level of participations twice (2012 and 2018) in preserving their heritage based on the ladder citizen participation approach. Also, it is to encourage community participation in order to promote city architecture conservation, heritage management, and sustainable development. The methodology followed in this empirical research involves using several data assembly methods such as structural observations, questionnaires, interviews, and mental mapping. The questionnaire was distributed among 92 local inhabitants aged 18-60 years. However, the outset of this research at the beginning demonstrated the majority negative attitude, motivation, and confidence of the local inhabitants’ role to safeguard their architectural heritage. Over time, there was a change in the negative attitudes. Therefore, raising public awareness and encouraging community participation by providing them with a real opportunity to take part in the decision-making. This may lead to a positive relationship between the community residents and the built heritage, which is essential for promoting its preservation and sustainable development.
Abstract: A growing list of cancers might be influenced by obesity. Obesity is associated with an increased risk for the occurrence and development of some cancers. Inflammation can lead to cancer. It is one of the characteristic features of cancer and plays a critical role in cancer development. C-reactive protein (CRP) is under evaluation related to the new and simple prognostic factors in patients with metastatic renal cell cancer. Obesity can predict and promote systemic inflammation in healthy adults. BMI is correlated with hs-CRP. In this study, SII index and CRP values were evaluated in children with normal BMI and those within the range of different obesity grades to detect the tendency towards cancer in pediatric obesity. A total of one hundred and ninety-four children; thirty-five children with normal BMI, twenty overweight (OW), forty-seven obese (OB) and ninety-two morbid obese (MO) participated in the study. Age- and sex-matched groups were constituted using BMI-for age percentiles. Informed consent was obtained. Ethical Committee approval was taken. Weight, height, waist circumference (C), hip C, head C and neck C of the children were measured. The complete blood count test was performed. C-reactive protein analysis was performed. Statistical analyses were performed using SPSS. The degree for statistical significance was p≤0.05. SII index values were progressively increasing starting from normal weight (NW) to MO children. There is a statistically significant difference between NW and OB as well as MO children. No significant difference was observed between NW and OW children, however, a correlation was observed between NW and OW children. MO constitutes the only group, which exhibited a statistically significant correlation between SII index and CRP. Obesity-related bladder, kidney, cervical, liver, colorectal, endometrial cancers are still being investigated. Obesity, characterized as a chronic low-grade inflammation, is a crucial risk factor for colon cancer. Elevated childhood BMI values may be indicative of processes leading to cancer, initiated early in life. Prevention of childhood adiposity may decrease the cancer incidence in adults. To authors’ best knowledge, this study is the first to introduce SII index values during obesity of varying degrees of severity. It is suggested that this index seems to affect all stages of obesity with an increasing tendency and may point out the concomitant status of obesity and cancer starting from very early periods of life.
Abstract: Application of reversible logic in integrated circuits results in the improved optimization of power consumption. This technology can be put into use in a variety of low power applications such as quantum computing, optical computing, nano-technology, and Complementary Metal Oxide Semiconductor (CMOS) Very Large Scale Integrated (VLSI) design etc. Logic gates are the basic building blocks in the design of any logic network and thus integrated circuits. In this paper, reversible Dual Key Gate (DKG) and Dual key Gate Pair (DKGP) gates that work singly as full adder/full subtractor are used to realize the basic building blocks of logic circuits. Reversible full adder/subtractor and parallel adder/ subtractor are designed using other reversible gates available in the literature and compared with that of DKG & DKGP gates. Efficient performance of reversible logic circuits relies on the optimization of the key parameters viz number of constant inputs, garbage outputs and number of reversible gates. The full adder/subtractor and parallel adder/subtractor design with reversible DKGP and DKG gates results in least number of constant inputs, garbage outputs, and number of reversible gates compared to the other designs. Thus, this paper provides a threshold to build more complex arithmetic systems using these reversible logic gates, leading to the enhanced performance of computing systems.
Abstract: The fault tolerant system plays a crucial role in the critical applications which are being used in the present scenario. A fault may change the functionality of circuits. Aim of this paper is to design multiplier using fault tolerant hybrid full adder. Fault tolerant hybrid full adder is designed to check and repair any fault in the circuit using self-checking circuit and the self-repairing circuit. Further, the use of conventional logic circuits may result in more area, delay as well as power consumption. In order to reduce these parameters of the circuit, GDI (Gate Diffusion Input) techniques with less number of transistors are used compared to conventional full adder circuit. This reduces the area, delay and power consumption. The proposed method solves the major problems occurring in the most crucial and critical applications.
Abstract: Recursive combination of an algorithm based on Karatsuba multiplication is exploited to design a generalized transpose and parallel Finite Impulse Response (FIR) Filter. Mid-range Karatsuba multiplication and Carry Save adder based on Karatsuba multiplication reduce time complexity for higher order multiplication implemented up to n-bit. As a result, we design modified N-tap Transpose and Parallel Symmetric FIR Filter Structure using Karatsuba algorithm. The mathematical formulation of the FFA Filter is derived. The proposed architecture involves significantly less area delay product (APD) then the existing block implementation. By adopting retiming technique, hardware cost is reduced further. The filter architecture is designed by using 90 nm technology library and is implemented by using cadence EDA Tool. The synthesized result shows better performance for different word length and block size. The design achieves switching activity reduction and low power consumption by applying with and without retiming for different combination of the circuit. The proposed structure achieves more than a half of the power reduction by adopting with and without retiming techniques compared to the earlier design structure. As a proof of the concept for block size 16 and filter length 64 for CKA method, it achieves a 51% as well as 70% less power by applying retiming technique, and for CSA method it achieves a 57% as well as 77% less power by applying retiming technique compared to the previously proposed design.
Abstract: The Carry Select Adder (CSLA) is a fast adder which improves the speed of addition. From the structure of the CSLA, it is clear that there is opportunity for reducing the area. The logic operations involved in conventional CSLA and binary to excess-1 converter (BEC) based CSLA are analyzed to make a study on the data dependence and to identify redundant logic operations. In the existing adder design, the carry select (CS) operation is scheduled before the final-sum, which is different from the conventional CSLA design. In the presented scheme, Kogge stone parallel adder approach is used instead of existing adder design it will generate fast carry for intermediate stages and also improves the speed of addition. When compared to existing adder design the delay is less in the proposed adder design.
Abstract: In a conventional network, most network devices, such as routers, are dedicated devices that do not have much variation in capacity. In recent years, a new concept of network functions virtualisation (NFV) has come into use. The intention is to implement a variety of network functions with software on general-purpose servers and this allows the network operator to select their capacities and locations without any constraints. This paper focuses on the allocation of NFV-based routing functions which are one of critical network functions, and presents the virtual routing function allocation algorithm that minimizes the total power consumption. In addition, this study presents the useful allocation policy of virtual routing functions, based on an evaluation with a ladder-shaped network model. This policy takes the ratio of the power consumption of a routing function to that of a circuit and traffic distribution between areas into consideration. Furthermore, the present paper shows that there are cases where the use of NFV-based routing functions makes it possible to reduce the total power consumption dramatically, in comparison to a conventional network, in which it is not economically viable to distribute small-capacity routing functions.
Abstract: Digital signal processor, image signal processor and FIR filters have multipliers as an important part of their design. On the basis of Vedic mathematics, Vedic multipliers have come out to be very fast multipliers. One of the image processing applications is edge detection. This research presents a small area and high speed 8 bit Vedic multiplier system comprising of compressor based adders. This results in faster edge detection. This architecture is tested on Xilinx vertex 4 FPGA board and simulations were carried out using the Xilinx synthesis tool. Comparisons are made and this system is found to be smaller in area with high speed (the lesser propagation delay). This compressor based Vedic multiplier is 1.1 times speedier than a typical Vedic multiplier. Also, this Vedic Multiplier is 2 times speedier than a ‘simple’ multiplier.
Abstract: A digital baseband Application-Specific Integrated Circuit (ASIC) (yclic Redundancy Checkis developed for a microchip transponder to transmit signals and temperature levels from biomedical monitoring devices. The transmission protocol is adapted from the ISO/IEC 11784/85 standard. The module has a decimation filter that employs only a single adder-subtractor in its datapath. The filtered output is coded with cyclic redundancy check and transmitted through backscattering Load Shift Keying (LSK) modulation to a reader. Fabricated using the 0.18-μm CMOS technology, the module occupies 0.116 mm2 in chip area (digital baseband: 0.060 mm2, decimation filter: 0.056 mm2), and consumes a total of less than 0.9 μW of power (digital baseband: 0.75 μW, decimation filter: 0.14 μW).
Abstract: An innovative approach to develop modified scaling free CORDIC based two parallel pipelined Multipath Delay Commutator (MDC) FFT and IFFT architectures for radix 22 FFT algorithm is presented. Multipliers and adders are the most important data paths in FFT and IFFT architectures. Multipliers occupy high area and consume more power. In order to optimize the area and power overhead, modified scaling-free CORDIC based complex multiplier is utilized in the proposed design. In general twiddle factor values are stored in RAM block. In the proposed work, modified scaling-free CORDIC based twiddle factor generator unit is used to generate the twiddle factor and efficient switching units are used. In addition to this, four point FFT operations are performed without complex multiplication which helps to reduce area and power in the last two stages of the pipelined architectures. The design proposed in this paper is based on multipath delay commutator method. The proposed design can be extended to any radix 2n based FFT/IFFT algorithm to improve the throughput. The work is synthesized using Synopsys design Compiler using TSMC 90-nm library. The proposed method proves to be better compared to the reference design in terms of area, throughput and power consumption. The comparative analysis of the proposed design with Xilinx FPGA platform is also discussed in the paper.
Abstract: This paper presents a fault-tolerant implementation for
adder schemes using the dual duplication code. To prove the
efficiency of the proposed method, the circuit is simulated in double
pass transistor CMOS 32nm technology and some transient faults are
voluntary injected in the Layout of the circuit. This fully differential
implementation requires only 20 transistors which mean that the
proposed design involves 28.57% saving in transistor count
compared to standard CMOS technology.
Abstract: This paper proposes techniques like MT CMOS,
POWER GATING, DUAL STACK, GALEOR and LECTOR to
reduce the leakage power. A Full Adder has been designed using
these techniques and power dissipation is calculated and is compared
with general CMOS logic of Full Adder.
Simulation results show the validity of the proposed techniques is
effective to save power dissipation and to increase the speed of
operation of the circuits to a large extent.
Abstract: The exposure to outdoor air pollution causes lung
cancer and increases the risk of bladder cancer. Because air pollution
in urban areas is mainly caused by transportation, it is necessary to
evaluate pollutant exhaust emissions from vehicles during their realworld
use. Nevertheless their evaluation and reduction is a key
problem, especially in the cities, that account for more than 50% of
world population.
A particular attention was given to the slope variability along the
streets during each journey performed by the instrumented vehicle.
In this paper we dealt with the problem of describing a
quantitatively approach for the reconstruction of GPS coordinates and
altitude, in the context of correlation study between driving cycles /
emission / geographical location, during an experimental campaign
realized with some instrumented cars.
Finally the slope analysis can be correlated to the emission and
consumption values in a specific road position, and it could be
evaluated its influence on their behaviour.
Abstract: In many communication and signal processing
systems, it is highly desirable to implement an efficient narrow-band
filter that decimate or interpolate the incoming signals. This paper
presents hardware efficient compensated CIC filter over a narrow
band frequency that increases the speed of down sampling by using
multiplierless decimation filters with polyphase FIR filter structure.
The proposed work analyzed the performance of compensated CIC
filter on the bases of the improvement of frequency response with
reduced hardware complexity in terms of no. of adders and
multipliers and produces the filtered results without any alterations.
CIC compensator filter demonstrated that by using compensation
with CIC filter improve the frequency response in passed of interest
26.57% with the reduction in hardware complexity 12.25%
multiplications per input sample (MPIS) and 23.4% additions per
input sample (APIS) w.r.t. FIR filter respectively.
Abstract: In this paper, we propose a new efficient reverse converter for the 4-moduli set {2n, 2n + 1, 2n − 1, 22n+1 – 1} based on a modified Chinese Remainder Theorem and Mixed Radix Conversion. Additionally, the resulting architecture is further reduced to obtain a reverse converter that utilizes only carry save adders, a multiplexer and carry propagate adders. The proposed converter has an area cost of (12n + 2) FAs and (5n + 1) HAs with a delay of (9n + 6)tFA + tMUX. When compared with state of the art, our proposal demonstrates to be faster, at the expense of slightly more hardware resources. Further, the Area-Time square metric was computed which indicated that our proposed scheme outperforms the state of the art reverse converter.
Abstract: An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high threshold voltage sleep transistor is used to reduce the static power dissipation in standby mode. The circuit is designed and simulated in TSPICE using TSMC 180nm CMOS process. Average power consumption, delay and power-delay product is measured which showed considerable improvement in performance over the existing full adder designs.